Shinichi Murai

According to our database, Shinichi Murai authored at least 12 papers between 1978 and 1993.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1993

Tri-state bus conflict checking method for ATPG using BDD.

Yasushi Koseko, Takuji Ogihara, Shinichi Murai

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1990

Rule-based testability rule check program.

Yasushi Koseko, C. Hiramine, Takuji Ogihara, Shinichi Murai

Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

1989

MULTES/IS: An Effective and Reliable Test Generation System for Partial Scan and Non-Scan Synchronous Circuits.

Takuji Ogihara, K. Muroi, Genichi Yonemori, Shinichi Murai

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988

Test generation for sequential circuits using individual initial value propagation.

Takuji Ogihara, Shuichi Saruyama, Shinichi Murai

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

1987

ASTA: LSI Design Management System.

Takuji Ogihara, H. Toyoshima, Shinichi Murai

Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

1985

LORES-2: A Logic Reorganization System.

Kiyoshi Enomoto, Shunichiro Nakamura, Takuji Ogihara, Shinichi Murai

IEEE Des. Test, 1985

PATEGE: an automatic DC parametric test generation system for series gated ECL circuits.

Takuji Ogihara, Shuichi Saruyama, Shinichi Murai

Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985

1983

Test generation for scan design circuits with tri-state modules and bidirectional terminals.

Takuji Ogihara, Shinichi Murai, Yuzo Takamatsu, Kozo Kinoshita, Hideo Fujiwara

Proceedings of the 20th Design Automation Conference, 1983

1981

An integrated computer aided design system for gate array masterslices: Part 2 the layout design system MARS-M3.

Chiyoji Tanaka, Shinichi Murai, Hiroo Tsuji, Toshihiko Yahara, Kaoru Okazaki, Masayuki Terai, Reiji Katoh, Mikio Tachibana

Proceedings of the 18th Design Automation Conference, 1981

An integrated computer aided design system for gate array masterslices: Part 1. Logic reorganization system LORES-2.

Chiyoji Tanaka, Shinichi Murai, Shunichiro Nakamura, Takuji Ogihara, Masayuki Terai, Kozo Kinoshita

Proceedings of the 18th Design Automation Conference, 1981

1979

A hierarchical placement procedure with a simple blocking scheme.

Shinichi Murai, Hiroo Tsuji, Morio Kakinuma, Kazumichi Sakaguchi, Chiyoji Tanaka

Proceedings of the 16th Design Automation Conference, 1979

1978

LORES - Logic Reorganization System.

Shunichiro Nakamura, Shinichi Murai, Chiyoji Tanaka, Masayuki Terai, Hideo Fujiwara, Kozo Kinoshita

Proceedings of the 15th Design Automation Conference, 1978