Shinichi Moriwaki

According to our database, Shinichi Moriwaki authored at least 7 papers between 2010 and 2013.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2013

Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges.

Shinji Miyano, Shinichi Moriwaki, Yasue Yamamoto, Atsushi Kawasumi, Toshikazu Suzuki, Takayasu Sakurai, Hirofumi Shinohara

IEEE J. Solid State Circuits, 2013

2012

A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges.

Shinichi Moriwaki, Yasuhiro Yamamoto, Atsushi Kawasumi, Toshikazu Suzuki, Shinji Miyano, Takayasu Sakurai, Hirofumi Shinohara

Proceedings of the Symposium on VLSI Circuits, 2012

A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme.

Shusuke Yoshimoto, Masaharu Terada, Youhei Umeki, Shunsuke Okumura, Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variations.

Yasue Yamamoto, Atsushi Kawasumi, Shinichi Moriwaki, Toshikazu Suzuki, Shinji Miyano, Hirofumi Shinohara

Proceedings of the 38th European Solid-State Circuit conference, 2012

2011

0.4V SRAM with bit line swing suppression charge share hierarchical bit line scheme.

Shinichi Moriwaki, Atsushi Kawasumi, Toshikazu Suzuki, Takayasu Sakurai, Shinji Miyano

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

Energy efficiency degradation caused by random variation in low-voltage SRAM and 26% energy reduction by Bitline Amplitude Limiting (BAL) scheme.

Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010

0.5-V, 150-MHz, bulk-CMOS SRAM with suspended bit-line read scheme.

Toshikazu Suzuki, Shinichi Moriwaki, Atsushi Kawasumi, Shinji Miyano, Hirofumi Shinohara

Proceedings of the 36th European Solid-State Circuits Conference, 2010