Shin'ichiro Okazaki

J. Signal Process. Syst., 2011

A dynamic SIMD/MIMD mode switching processor for embedded real-time image recognition systems.

[BibT_eX]

[DOI]

Shouhei Nomoto

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010

Performance Evaluation of a Dynamically Switchable SIMD/MIMD Processor by Using an Image Recognition Application.

[BibT_eX]

[DOI]

Shouhei Nomoto

IPSJ Trans. Syst. LSI Des. Methodol., 2010

2009

Mapping schemes of image recognition tasks onto highly parallel SIMD/MIMD processors.

[BibT_eX]

[DOI]

Shouhei Nomoto

Proceedings of the Third ACM/IEEE International Conference on Distributed Smart Cameras, 2009

IMAPCAR2: A dynamic SIMD/MIMD mode switching processor for embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 2009 IEEE Hot Chips 21 Symposium (HCS), 2009

2008

Overtaking Vehicle Detection Method and Its Implementation Using IMAPCAR Highly Parallel Image Processor.

[BibT_eX]

[DOI]

Kazuyuki Sakurai

IEICE Trans. Inf. Syst., 2008

In-vehicle vision processors for driver assistance systems.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

An Integrated Memory Array Processor for Embedded Image Recognition Systems.

[BibT_eX]

[DOI]

Tamio Arai

IEEE Trans. Computers, 2007

A low-cost mixed-mode parallel processor architecture for embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 21th Annual International Conference on Supercomputing, 2007

2005

An Integrated Memory Array Processor Architecture for Embedded Image Recognition Systems.

[BibT_eX]

[DOI]

Tamio Arai

Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

2004

A 51.2 GOPS Programmable Video Recognition Processor for Vision-Based Intelligent Cruise Control Applications.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2004

2003

A 51.2-GOPS scalable video recognition processor for intelligent cruise control based on a linear array of 128 four-way VLIW processing elements.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2003

2001

IMAP-CE: a 51.2 GOPS video rate image processor with 128 VLIW processing elements.

[BibT_eX]

[DOI]

Takuya Koga

Proceedings of the 2001 International Conference on Image Processing, 2001

1996

A 3.84 gips integrated memory array processor.

[BibT_eX]

[DOI]

Syst. Comput. Jpn., 1996

IMAP-VISION: An SIMD Processor with High-Speed On-chip Memory and Large Capacity External Memory.

[BibT_eX]

[DOI]

Proceedings of IAPR Workshop on Machine Vision Applications, 1996

An integrated memory array processor with a synchronous-DRAM interface for real-time vision applications.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on Pattern Recognition, 1996

1995

Design of 1.28-GB/s high bandwidth 2-Mb SRAM for integrated memory array processor applications.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, June, 1995

A compact real-time vision system using integrated memory array processor architecture.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 1995

1994

A 3.84 GIPS integrated memory array processor with 64 processing elements and a 2-Mb SRAM.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, November, 1994

A real-time vision system using an integrated memory array processor prototype.

[BibT_eX]

[DOI]

Mach. Vis. Appl., 1994

A Compact 30GIPS Real-Time Vision System RVS-2.

[BibT_eX]

[DOI]

Proceedings of IAPR Workshop on Machine Vision Applications, 1994

1993

Dataflow Graph Optimization for Dataflow Architectures - A Dataflow Optimizing Compiler.

[BibT_eX]

[DOI]

Sholin Kyo

Masanori Mizoguchi

Proceedings of the 1993 International Conference on Parallel Processing, 1993

1992

Imap: Integrated Memory Array Processor.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 1992

A Real-Time Vision System Using Integrated Memory Array Processor Prototype LSI.

[BibT_eX]

[DOI]

Proceedings of IAPR Workshop on Machine Vision Applications, 1992

1988

Knowledge-Based Approach for Adaptive Recognition of Drawings.

[BibT_eX]

[DOI]