Shin'ichiro Kimura

According to our database¹, Shin'ichiro Kimura authored at least 3 papers between 1997 and 2002.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of five.

Awards

IEEE Fellow

IEEE Fellow 2011, "For contributions to advanced stack memory cells for high density dynamic randon access memories".

Timeline

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In proceedings

Article

PhD thesis

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Links

On csauthors.net:

Bibliography

2002

Reliability issues of silicon LSIs facing 100-nm technology node.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2002

1999

A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 1999

1997

Limitations and challenges of multigigabit DRAM chip design.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 1997

Shin'ichiro Kimura

Awards

IEEE Fellow

Timeline

Legend:

Links

On csauthors.net:

Bibliography

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