Shin'ichi Wakabayashi
Orcid: 0000-0003-0378-7657
According to our database1,
Shin'ichi Wakabayashi
authored at least 61 papers
between 1985 and 2024.
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Bibliography
2024
A Proposal of Equivalence Classes in Maximally Asymmetric Functions and Their Application to Benchmark Generation.
Proceedings of the 54th IEEE International Symposium on Multiple-Valued Logic, 2024
Enhancing Security of Generalization Methods Based on m-Invariance for Dynamic Data Publication.
Proceedings of the 48th IEEE Annual Computers, Software, and Applications Conference, 2024
2023
IPSJ Trans. Syst. LSI Des. Methodol., 2023
2022
Introduction of a New Method for Preventing Recipient Unapproved Transactions to Bitcoin Wallet.
Proceedings of the 46th IEEE Annual Computers, Software, and Applications Conferenc, 2022
2021
A Protocol for Preventing Transaction Commitment Without Recipient's Authorization on Blockchain and It's Implementation.
IEEE Access, 2021
2020
Proceedings of the 44th IEEE Annual Computers, Software, and Applications Conference, 2020
A Framework for Fast MapReduce Processing Considering Sensitive Data on Hybrid Clouds.
Proceedings of the 44th IEEE Annual Computers, Software, and Applications Conference, 2020
2019
A Protocol for Preventing Transaction Commitment without Recipient's Authorization on Blockchain.
Proceedings of the 43rd IEEE Annual Computer Software and Applications Conference, 2019
2018
Proceedings of the International Conference on Field-Programmable Technology, 2018
Novel Feature Vectors Considering Distances between Wires for Lithography Hotspot Detection.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018
Proceedings of the Database and Expert Systems Applications, 2018
2016
An efficient FPGA implementation of Mahalanobis distance-based outlier detection for streaming data.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016
2015
Inter-FPGA Routing for Partially Time-Multiplexing Inter-FPGA Signals on Multi-FPGA Systems with Various Topologies.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015
2014
An Area Efficient Regular Expression Matching Engine Using Partial Reconfiguration for Quick Pattern Updating.
IPSJ Trans. Syst. LSI Des. Methodol., 2014
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014
2013
A Flexible and Compact Regular Expression Matching Engine Using Partial Reconfiguration for FPGA.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
2011
An Efficient Hardware Matching Engine for Regular Expression with Nested Kleene Operators.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011
A Design Method for Programmable Two-Variable Discrete Function Generators Using Spline and Bilinear Interpolations.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011
2010
Proceedings of the International Conference on Field-Programmable Technology, 2010
2009
A Systolic String Matching Algorithm for High-Speed Recognition of a Restricted Regular Set.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009
2008
A systolic regular expression pattern matching engine and its application to network intrusion detection.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008
2007
A Parallel Multistage Metaheuristic Algorithm for VLSI Floorplanning.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2007
A Systolic Algorithm for the Quadratic Assignment Problem and its FPGA Implementation.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007
2006
Proceedings of the 22nd International Conference on Data Engineering Workshops, 2006
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006
2005
Proceedings of the 15th International Workshop on Research Issues in Data Engineering (RIDE-SDMA 2005), 2005
Proceedings of the 21st International Conference on Data Engineering Workshops, 2005
Proceedings of the 21st International Conference on Data Engineering Workshops, 2005
Solving the Minimum Dominating Set Problem with Instance-Specific Hardware on FPGAs.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005
2004
Proceedings of the Field Programmable Logic and Application, 2004
2002
A coterie-based mutual exclusion algorithm for distributed systems allowing multiple process failures at arbitrary time.
Syst. Comput. Jpn., 2002
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002
A hierarchical standard cell placement method based on a new cluster placement model.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002
2001
Adaptation of genetic operators and parameters of a genetic algorithm based on the elite degree of an individual.
Syst. Comput. Jpn., 2001
2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer.
Proceedings of ASP-DAC 2000, 2000
1999
A timing-driven floorplanning algorithm with the Elmore delay model for building block layout.
Integr., 1999
An LSI Implementation of an Adaptive Genetic Algorithm with On-The Fly Crossover Operator Selection.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999
1998
Solving the Capacitor Placement Problem in a Radial Distribution System Using an Adaptive Genetic Algorithm.
Proceedings of the Parallel Problem Solving from Nature, 1998
A Timing-Driven Global Routing Algorithm with Pin Assignment, Block Reshaping, and Positioning for Building Block Layout.
Proceedings of the ASP-DAC '98, 1998
1997
Integr., 1997
Par-POPINS: a timing-driven parallel placement method with the Elmore delay model for row based VLSIs.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997
1996
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996
1995
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995
A new performance driven placement method with the Elmore delay model for row based VLSIs.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995
A new system partitioning method under performance and physical constraints for multi-chip modules.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995
1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
1993
Gate Array Placement Based on Mincut, Partitioning with Path Delay Constraints.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
Proceedings of the European Design Automation Conference 1993, 1993
1992
Proceedings of the conference on European design automation, 1992
1989
Proceedings of the IEEE Workshop on Visual Languages, 1989
1985