Shin-ichi O'Uchi
Orcid: 0000-0002-9386-3571
According to our database1,
Shin-ichi O'Uchi
authored at least 23 papers
between 2002 and 2022.
Collaborative distances:
Collaborative distances:
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Bibliography
2022
Low-Precision Quantization Techniques for Hardware-Implementation-Friendly BERT Models.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022
Short Floating-Point CNN Accelerator for Brain-Computer Interface to Decode Visual Information.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2019
Proceedings of the International Joint Conference on Neural Networks, 2019
2018
Image-Classifier Deep Convolutional Neural Network Training by 9-bit Dedicated Hardware to Realize Validation Accuracy and Energy Efficiency Superior to the Half Precision Floating Point Format.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Fully Integrated, 100-mV Minimum Input Voltage Converter With Gate-Boosted Charge Pump Kick-Started by LC Oscillator for Energy Harvesting.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
2015
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
2014
SOI CMOS Voltage Multiplier Circuits with Body Bias Control Technique for Battery-Less Wireless Sensor System.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
Improvement of epitaxial channel quality on heavily arsenic- and boron-doped Si surfaces and impact on tunnel FET performance.
Proceedings of the 44th European Solid State Device Research Conference, 2014
Variation behavior of tunnel-FETs originated from dopant concentration at source region and channel edge configuration.
Proceedings of the 44th European Solid State Device Research Conference, 2014
2013
Performance limit of parallel electric field tunnel FET and improvement by modified gate and channel configurations.
Proceedings of the European Solid-State Device Research Conference, 2013
Guidelines for symmetric threshold voltage in tunnel FinFETs with single and dual metal gate electrodes.
Proceedings of the European Solid-State Device Research Conference, 2013
2012
IEICE Trans. Electron., 2012
IEICE Trans. Electron., 2012
2010
0.5V FinFET SRAM with dynamic threshold control of pass gates for salvaging malfunctioned bits.
Proceedings of the 36th European Solid-State Circuits Conference, 2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2008
IEICE Trans. Electron., 2008
2007
Flex-Pass-Gate SRAM Design for Static Noise Margin Enhancement Using FinFET-Based Technology.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002