Shin'ichi Kobayashi
According to our database1,
Shin'ichi Kobayashi
authored at least 5 papers
between 1992 and 2006.
Collaborative distances:
Collaborative distances:
Timeline
1992
1994
1996
1998
2000
2002
2004
2006
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1
2
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2006
Proceedings of the 39th Hawaii International International Conference on Systems Science (HICSS-39 2006), 2006
2005
Proceedings of the Advances in Knowledge Discovery and Data Mining, 2005
1998
A Functional Model of Cortico-Basal Ganglia Loop in Motor Control.
Proceedings of the Fifth International Conference on Neural Information Processing, 1998
1994
Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory.
IEEE J. Solid State Circuits, April, 1994
1992
A new erasing and row decoding scheme for low supply voltage operation 16-Mb/64-Mb flash memories.
IEEE J. Solid State Circuits, April, 1992