Shin'ichi Ikenaga

According to our database, Shin'ichi Ikenaga authored at least 3 papers between 1988 and 1990.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1990

A tunable CMOS-DRAM voltage limiter with stabilized feedback amplifier.

Masashi Horiguchi, Masakazu Aoki, Jun Etoh, Hitoshi Tanaka, Shin'ichi Ikenaga, Kiyoo Itoh, Kazuhiko Kajigaya, Hiroaki Kotani, Kazuyoshi Ohshima, Tetsuro Matsumoto

IEEE J. Solid State Circuits, October, 1990

1989

New DRAM noise generation under half-V_cc precharge and its reduction using a transposed amplifier.

Masakazu Aoki, Shin'ichi Ikenaga, Yoshinobu Nakagome, Masashi Horiguchi, Yasushi Kawase, Yoshifumi Kawamoto, Kiyoo Itoh

IEEE J. Solid State Circuits, August, 1989

1988

An experimental large-capacity semiconductor file memory using 16-levels/cell storage.

Masashi Horiguchi, Masakazu Aoki, Yoshinobu Nakagome, Shin'ichi Ikenaga, Katsuhiro Shimohigashi

IEEE J. Solid State Circuits, February, 1988