Shin-Hyun Jeong

According to our database, Shin-Hyun Jeong authored at least 7 papers between 2019 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

An N/PBTI-Isolated BTI Monitor With a Configurable Switching Network and Calibration for Process Variation in Memory Periphery.

Shin-Hyun Jeong, Yong-Un Jeong, Suhwan Kim

IEEE Trans. Circuits Syst. II Express Briefs, November, 2024

2022

A 10 Gb/s/pin Single-Ended Transmitter With Reflection-Aided Duobinary Modulation for Dual-Rank Mobile Memory Interfaces.

Yong-Un Jeong, Sungphil Choi, Joo-Hyung Chae, Jaekwang Yun, Shin-Hyun Jeong, Suhwan Kim

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

2021

A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface.

Yong-Un Jeong, Hyunkyu Park, Changho Hyun, Joo-Hyung Chae, Shin-Hyun Jeong, Suhwan Kim

IEEE J. Solid State Circuits, 2021

A Differentiating Receiver With a Transition-Detecting DFE for Dual-Rank Mobile Memory Interface.

Sungphil Choi, Yong-Un Jeong, Joo-Hyung Chae, Shin-Hyun Jeong, Suhwan Kim

IEEE Access, 2021

A High-Accuracy and Fast-Correction Quadrature Signal Corrector Using an Adaptive Delay Gain Controller for Memory Interfaces.

Hyunkyu Park, Jihwan Park, Jae-Whan Lee, Yong-Un Jeong, Shin-Hyun Jeong, Suhwan Kim, Joo-Hyung Chae

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020

A 0.4-1.7GHz Wide Range Fractional-N PLL Using a Transition-Detection DAC for Jitter Reduction.

Jaekwang Yun, Sangyoon Lee, Yong-Un Jeong, Shin-Hyun Jeong, Suhwan Kim

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020

2019

A Low-Power and Low-Noise 20: 1 Serializer with Two Calibration Loops in 55-nm CMOS.

Yong-Un Jeong, Joo-Hyung Chae, Sungphil Choi, Jaekwang Yun, Shin-Hyun Jeong, Suhwan Kim

Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019