Shimpei Sato
Orcid: 0000-0003-0292-1391
According to our database1,
Shimpei Sato
authored at least 53 papers
between 2009 and 2024.
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Bibliography
2024
Direct Data-Driven Control-Based Additive Feedforward Compensation for Fast and Precise Positioning Control.
Proceedings of the IEEE International Conference on Advanced Intelligent Mechatronics, 2024
On Relation Between Leakage-Free Condition and Differential Filtering Order in ETFE-Based Frequency Responce Function Estimation<sup>*</sup>.
Proceedings of the IEEE International Conference on Advanced Intelligent Mechatronics, 2024
2023
Humanoid Walking System with CNN-Based Uneven Terrain Recognition and Landing Control with Swing-Leg Velocity Constraints.
IROS, 2023
Whole-Body Torque Control Without Joint Position Control Using Vibration-Suppressed Friction Compensation for Bipedal Locomotion of Gear-Driven Torque Sensorless Humanoid.
IROS, 2023
2022
Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2022
Trajectory Generation and Compensation for External Forces with a Leg-wheeled Robot Designed for Human Passengers.
Proceedings of the 21st IEEE-RAS International Conference on Humanoid Robots, 2022
2021
Energy-Efficient ECG Signals Outlier Detection Hardware Using a Sparse Robust Deep Autoencoder.
IEICE Trans. Inf. Syst., 2021
IEICE Trans. Inf. Syst., 2021
Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2021
2020
SENTEI: Filter-Wise Pruning with Distillation towards Efficient Sparse Convolutional Neural Network Accelerators.
IEICE Trans. Inf. Syst., 2020
A Fast Length Matching Routing Pattern Generation Method for Set-Pair Routing Problem Using Selective Pin-Pair Connections.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020
Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020
Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, 2020
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020
2019
Power Efficient Object Detector with an Event-Driven Camera for Moving Object Surveillance on an FPGA.
IEICE Trans. Inf. Syst., 2019
A Low Area Overhead Design Method for High-Performance General-Synchronous Circuits with Speculative Execution.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019
GUINNESS: A GUI Based Binarized Deep Neural Network Framework for Software Programmers.
IEICE Trans. Inf. Syst., 2019
FPGA-based Accurate Pedestrian Detection with Thermal Camera for Surveillance System.
Proceedings of the 2019 International Conference on ReConFigurable Computing and FPGAs, 2019
Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019
Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019
A Low Area Overhead Design for High-Performance General-Synchronous Circuits with Speculative Execution.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
FPGA-Based Training Accelerator Utilizing Sparseness of Convolutional Neural Network.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019
2018
BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W.
IEEE J. Solid State Circuits, 2018
IEICE Trans. Inf. Syst., 2018
An FPGA Realization of a Random Forest with <i>k</i>-Means Clustering Using a High-Level Synthesis Design.
IEICE Trans. Inf. Syst., 2018
IEICE Trans. Inf. Syst., 2018
Pattern Similarity Metrics for Layout Pattern Classification and Their Validity Analysis by Lithographic Responses.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
A Ternary Weight Binary Input Convolutional Neural Network: Realization on the Embedded Processor.
Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018
Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2018
A Performance Per Power Efficient Object Detector on an FPGA for Robot Operating System (ROS).
Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2018
A Tri-State Weight Convolutional Neural Network for an FPGA: Applied to YOLOv2 Object Detector.
Proceedings of the International Conference on Field-Programmable Technology, 2018
An FPGA Realization of OpenPose Based on a Sparse Weight Convolutional Neural Network.
Proceedings of the International Conference on Field-Programmable Technology, 2018
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018
A Lightweight YOLOv2: A Binarized CNN with A Parallel Support Vector Regression for an FPGA.
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018
2017
Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGA.
ACM Trans. Reconfigurable Technol. Syst., 2017
In-memory area-efficient signal streaming processor design for binary neural networks.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the International Conference on Field Programmable Technology, 2017
An object detector based on multiscale sliding window search using a fully pipelined binarized CNN on an FPGA.
Proceedings of the International Conference on Field Programmable Technology, 2017
A fully connected layer elimination for a binarizec convolutional neural network on an FPGA.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017
2015
Investigating potential performance benefits of memory layout optimization based on roofline model.
Proceedings of the 2nd International Workshop on Software Engineering for Parallel Systems, 2015
Exana: an execution-driven application analysis tool for assisting productive performance tuning.
Proceedings of the 2nd International Workshop on Software Engineering for Parallel Systems, 2015
Proceedings of the Third International Symposium on Computing and Networking, 2015
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015
Enabling Fast and Accurate Emulation of Large-Scale Network on Chip Architectures on a Single FPGA.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015
2014
Proceedings of the IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, 2014
2013
2010
Proceedings of the First International Conference on Networking and Computing, 2010
Proceedings of the First International Conference on Networking and Computing, 2010
2009
Inf. Media Technol., 2009
Proceedings of the 2009 International Conference on Parallel and Distributed Computing, 2009