Shijia Wei

Orcid: 0000-0002-4513-5334

According to our database1, Shijia Wei authored at least 11 papers between 2019 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2024
Obsidian: Cooperative State-Space Exploration for Performant Inference on Secure ML Accelerators.
CoRR, 2024

SoK Paper: Power Side-Channel Malware Detection.
Proceedings of the 13th International Workshop on Hardware and Architectural Support for Security and Privacy, 2024

2023
Sidecars on the Central Lane: Impact of Network Proxies on Microservices.
CoRR, 2023

2022
Revisiting Browser Performance Benchmarking From an Architectural Perspective.
IEEE Comput. Archit. Lett., 2022

2021
Software-driven Security Attacks: From Vulnerability Sources to Durable Hardware Defenses.
ACM J. Emerg. Technol. Comput. Syst., 2021

Bandwidth Utilization Side-Channel on ML Inference Accelerators.
CoRR, 2021

Morpheus II: A RISC-V Security Extension for Protecting Vulnerable Software and Hardware.
Proceedings of the IEEE Hot Chips 33 Symposium, 2021

Morpheus II: A RISC-V Security Extension for Protecting Vulnerable Software and Hardware.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2021

2020
SESAME: Software defined Enclaves to Secure Inference Accelerators with Multi-tenant Execution.
CoRR, 2020

2019
Cyclone: Detecting Contention-Based Cache Information Leaks Through Cyclic Interference.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

Using Power-Anomalies to Counter Evasive Micro-Architectural Attacks in Embedded Systems.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019


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