Shihui Yin
Orcid: 0000-0001-7186-0946
According to our database1,
Shihui Yin
authored at least 43 papers
between 2014 and 2023.
Collaborative distances:
Collaborative distances:
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Bibliography
2023
PIMCA: A Programmable In-Memory Computing Accelerator for Energy-Efficient DNN Inference.
IEEE J. Solid State Circuits, May, 2023
2022
Neuromorph. Comput. Eng., December, 2022
IEEE Des. Test, 2022
Vertical Channel-All-Around (CAA) IGZO FET under 50 nm CD with High Read Current of 32.8 μA/μm (Vth + 1 V), Well-performed Thermal Stability up to 120 ℃ for Low Latency, High-density 2T0C 3D DRAM Application.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Compact Modeling of IGZO-based CAA-FETs with Time-zero-instability and BTI Impact on Device and Capacitor-less DRAM Retention Reliability.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
2021
PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Characterization and Mitigation of Relaxation Effects on Multi-level RRAM based In-Memory Computing.
Proceedings of the IEEE International Reliability Physics Symposium, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Leveraging Noise and Aggressive Quantization of In-Memory Computing for Robust DNN Hardware Against Adversarial Input and Weight Attacks.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
2020
PhD thesis, 2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
ECG Authentication Hardware Design With Low-Power Signal Processing and Neural Network Optimization With Low Precision and Structured Compression.
IEEE Trans. Biomed. Circuits Syst., 2020
IEEE J. Solid State Circuits, 2020
An 8.93 TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity for On-Device Speech Recognition.
IEEE J. Solid State Circuits, 2020
C3SRAM: An In-Memory-Computing SRAM Macro Based on Robust Capacitive Coupling Computing Mechanism.
IEEE J. Solid State Circuits, 2020
A Smart Hardware Security Engine Combining Entropy Sources of ECG, HRV, and SRAM PUF for Authentication and Secret Key Generation.
IEEE J. Solid State Circuits, 2020
Proceedings of the International SoC Design Conference, 2020
Proceedings of the Twenty-Ninth International Joint Conference on Artificial Intelligence, 2020
FPGA-based Low-Batch Training Accelerator for Modern CNNs Featuring High Bandwidth Memory.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
An On-Chip Learning Accelerator for Spiking Neural Networks using STT-RAM Crossbar Arrays.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning.
IEEE Micro, 2019
A 1.06- $\mu$ W Smart ECG Processor in 65-nm CMOS for Real-Time Biometric Authentication and Personal Cardiac Monitoring.
IEEE J. Solid State Circuits, 2019
High-Throughput In-Memory Computing for Binary Deep Neural Networks with Monolithically Integrated RRAM and 90nm CMOS.
CoRR, 2019
Proceedings of the International Symposium on Memory Systems, 2019
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
ECG Authentication Neural Network Hardware Design with Collective Optimization of Low Precision and Structured Compression.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Neuromorphic Hardware Accelerator for SNN Inference based on STT-RAM Crossbar Arrays.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Joint Optimization of Quantization and Structured Sparsity for Compressed Deep Neural Networks.
Proceedings of the IEEE International Conference on Acoustics, 2019
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
Proceedings of the 53rd Asilomar Conference on Signals, Systems, and Computers, 2019
2018
Environment-Adaptable Fast Multi-Resolution (EAF-MR) optimization in large-scale RF-FPGA systems.
EURASIP J. Wirel. Commun. Netw., 2018
A Parallel RRAM Synaptic Array Architecture for Energy-Efficient Recurrent Neural Networks.
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018
XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
Proceedings of the 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2017
Algorithm and hardware design of discrete-time spiking neural networks based on back propagation with binary activations.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017
Minimizing area and energy of deep learning hardware design using collective low precision and structured compression.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017
2016
Re-thinking polynomial optimization: Efficient programming of reconfigurable radio frequency (RF) systems by convexification.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
Phase Noise Impairment and Environment-Adaptable Fast (EAF) Optimization for Programming of Reconfigurable Radio Frequency (RF) Receivers.
Proceedings of the 2015 IEEE Global Communications Conference, 2015
Accurate passivity-enforced macromodeling for RF circuits via iterative zero/pole update based on measurement data.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
Environment-Adaptable Efficient Optimization for Programming of Reconfigurable Radio Frequency (RF) Receivers.
Proceedings of the 2014 IEEE Military Communications Conference, 2014