Shiheng Yang

Orcid: 0000-0002-4883-160X

According to our database1, Shiheng Yang authored at least 18 papers between 2014 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
A Compact Sub-nW/kHz Relaxation Oscillator Using a Negative-Offset Comparator With Chopping and Piecewise Charge-Acceleration in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2024

2023
A 0.0043-mm<sup>2</sup> 0.085-μW/MHz Relaxation Oscillator Using Charge-Prestored Asymmetric Swings R-RC Network.
IEEE Trans. Very Large Scale Integr. Syst., August, 2023

On the DC-Settling Process of the Pierce Crystal Oscillator in Start-Up.
IEEE Trans. Circuits Syst. II Express Briefs, 2023

2022
Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A 4.2-to-5.6 GHz Transformer-Based PMOS-only Stacked-gm VCO in 28-nm CMOS.
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

2021
A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Sampling and Comparator Speed-Enhancement Techniques for Near-Threshold SAR ADCs.
IEEE Open J. Circuits Syst., 2021

A Low-Power RC Oscillator with Offset and Path Delay Cancellation.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

A 640×512 30μm Pixel Pitch 1.8mK-NETD 90.1dB-SNR Digital Read-out Integrated Circuit with Fully On-chip Image Algorithm Pixel-Level Calibration.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

A Low Power Sample-and-Hold Circuit with Improved Dynamic Bias for Pipelined ADC.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2021

2020
A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector.
IEEE Access, 2020

2019
A 0.12-mm<sup>2</sup> 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N Bang-Bang Digital PLL With 8-µs Settling Time for Multi-ISM-Band ULP Radios.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A 0.2-V Energy-Harvesting BLE Transmitter With a Micropower Manager Achieving 25% System Efficiency at 0-dBm Output and 5.2-nW Sleep Power in 28-nm CMOS.
IEEE J. Solid State Circuits, 2019

A 0.0056-mm<sup>2</sup> -249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring VCOs.
IEEE J. Solid State Circuits, 2019

A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
A 0.2V energy-harvesting BLE transmitter with a micropower manager achieving 25% system efficiency at 0dBm output and 5.2nW sleep power in 28nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A 0.0056mm<sup>2</sup> all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrms Jitter and -249dB FOM.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2014
A 104μW EMI-resisting bandgap voltage reference achieving -20dB PSRR, and 5% DC shift under a 4dBm EMI level.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014


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