Shih Ping Lin

According to our database, Shih Ping Lin authored at least 7 papers between 2002 and 2007.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2007

A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design.

Shih-Ping Lin, Chung-Len Lee, Jwu-E Chen, Ji-Jan Chen, Kun-Lun Luo, Wen Ching Wu

IEEE Trans. Very Large Scale Integr. Syst., 2007

2006

A Multilayer Data Copy Scheme for Low Cost Test with Controlled Scan-In Power for Multiple Scan Chain Designs.

Shih Ping Lin, Chung-Len Lee, Jwu E. Chen, Ji-Jan Chen, Kun-Lun Luo, Wen Ching Wu

Proceedings of the 2006 IEEE International Test Conference, 2006

2005

Adaptive Encoding Scheme for Test Volume/Time Reduction in SoC Scan Testing.

Shih Ping Lin, Chung-Len Lee, Jwu E. Chen

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

A Scan Matrix Design for Low Power Scan-Based Test.

Shih Ping Lin, Chung-Len Lee, Jwu E. Chen

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

MR: a new framework for multilevel full-chip routing.

Yao-Wen Chang, Shih-Ping Lin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

2003

Corner sequence - a P-admissible floorplan representation with a worst case linear-time packing scheme.

Jai-Ming Lin, Yao-Wen Chang, Shih-Ping Lin

IEEE Trans. Very Large Scale Integr. Syst., 2003

2002

A novel framework for multilevel routing considering routability and performance.

Shih-Ping Lin, Yao-Wen Chang

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002