Shih-Arn Hwang

According to our database, Shih-Arn Hwang authored at least 7 papers between 1998 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

14.4 A Fully Digital Current Sensor Offering Per-Core Runtime Power for System Budgeting in a 4nm-Plus Octa-Core CPU.

Chien-Yu Lu, Bo-Jr Huang, Min-Chieh Chen, Ollie Tsai, Alfred Tsai, Eric Jia-Wei Fang, Yuju Cho, Harry H. Chen, Ping Kao, Ericbill Wang, Hugh Mair, Shih-Arn Hwang

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023

A 5G Mobile Gaming-Centric SoC with High-Performance Thermal Management in 4nm FinFET.

Bo-Jr Huang, Alfred Tsai, Lear Hsieh, Kathleen Chang, C.-J. Tsai, Jia-Ming Chen, Eric Jia-Wei Fang, Sung S.-Y. Hsueh, Jack Ciao, Barry Chen, Chuck Chang, Ping Kao, Ericbill Wang, Harry H. Chen, Hugh Mair, Shih-Arn Hwang

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022

A 5nm 3.4GHz Tri-Gear ARMv9 CPU Subsystem in a Fully Integrated 5G Flagship Mobile SoC.

Ashish Nayak, HsinChen Chen, Hugh Mair, Rolf Lagerquist, Tao Chen, Anand Rajagopalan, Gordon Gammie, Ramu Madhavaram, Madhur Jagota, C. J. Chung, Jenny Wiedemeier, Bala Meera, Chao-Yang Yeh, Maverick Lin, Curtis Lin, Vincent Lin, Jiun Lin, Y. S. Chen, Barry Chen, Cheng-Yuh Wu, Ryan ChangChien, Ray Tzeng, Kelvin Yang, Achuta Thippana, Ericbill Wang, Shih-Arn Hwang

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2021

35.1 An Octa-Core 2.8/2GHz Dual-Gear Sensor-Assisted High-Speed and Power-Efficient CPU in 7nm FinFET 5G Smartphone SoC.

Bo-Jr Huang, Eric Jia-Wei Fang, Sung S.-Y. Hsueh, Rory Huang, Angus Lin, Chi-Hsun Chiang, Yi-Hsuan Lin, Wen-Wen Hsieh, Barry Chen, Yi-Chang Zhuang, Cheng-Yuh Wu, Jia-Ming Chen, Y. S. Chen, Cheng-Tien Wan, Ericbill Wang, Alex Chiou, Ping Kao, Yuwen Tsai, Harry H. Chen, Shih-Arn Hwang

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2001

Unified VLSI systolic array design for LZ data compression.

Shih-Arn Hwang, Cheng-Wen Wu

IEEE Trans. Very Large Scale Integr. Syst., 2001

1999

Test Energy Minimization for C-Testable ILAs.

Shih-Arn Hwang, Cheng-Wen Wu

J. Inf. Sci. Eng., 1999

1998

Sequential circuit fault simulation using logic emulation.

Shih-Arn Hwang, Jin-Hua Hong, Cheng-Wen Wu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998