Shigeyoshi Watanabe

According to our database, Shigeyoshi Watanabe authored at least 29 papers between 1989 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2017

The Performance Evaluation of a 3D Torus Network Using Partial Link-Sharing Method in NoC Router Buffer.

Naohisa Fukase, Yasuyuki Miura, Shigeyoshi Watanabe, M. M. Hafizur Rahman

IEICE Trans. Inf. Syst., 2017

2016

The performance evaluation of 3D torus using link-sharing method in NoC router.

Naohisa Fukase, Yasuyuki Miura, Shigeyoshi Watanabe, M. M. Hafizur Rahman

Proceedings of the IEEE International Conference on Consumer Electronics-Taiwan, 2016

2015

An Adaptive Routing Algorithm of 2-D Torus Network Based on Turn Model: The Communication Performance.

Yasuyuki Miura, Kentaro Shimozono, Naohisa Fukase, Shigeyoshi Watanabe, Kazuya Matoyama

Int. J. Netw. Comput., 2015

2014

Reconfigurable Circuit Design Based on Arithmetic Logic Unit Using Double-Gate CNTFETs.

Hiroshi Ninomiya, Manabu Kobayashi, Yasuyuki Miura, Shigeyoshi Watanabe

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Reconfigurable Dynamic Logic Circuit Generating <i>t</i>-Term Boolean Functions Based on Double-Gate CNTFETs.

Manabu Kobayashi, Hiroshi Ninomiya, Yasuyuki Miura, Shigeyoshi Watanabe

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

The Proposal of Partial Sharing for Link-Sharing Method of Buffer in NoC Router.

Naohisa Fukase, Yasuyuki Miura, Shigeyoshi Watanabe, M. M. Hafizur Rahman

Proceedings of the Second International Symposium on Computing and Networking, 2014

2013

Analysis of emission right prices in greenhouse gas emission trading via agent-based model.

Tomohiro Nakada, Keiki Takadama, Shigeyoshi Watanabe

Multiagent Grid Syst., 2013

Reduced Reconfigurable Logic Circuit Design Based on Double Gate CNTFETs Using Ambipolar Binary Decision Diagram.

Hiroshi Ninomiya, Manabu Kobayashi, Shigeyoshi Watanabe

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Circuit Design of Reconfigurable Logic Based on Double-Gate CNTFETs.

Manabu Kobayashi, Hiroshi Ninomiya, Shigeyoshi Watanabe

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

An Adaptive Routing of the 2-D Torus Network Based on Turn Model.

Yasuyuki Miura, Kazuya Matoyama, Kentaro Shimozono, Shigeyoshi Watanabe

Proceedings of the First International Symposium on Computing and Networking, 2013

2010

Foreword.

Shigeyoshi Watanabe

IEICE Trans. Electron., 2010

Adaptive routing algorithms and implementation for interconnection network TESH for parallel processing.

Yasuyuki Miura, Masahiro Kaneko, Shigeyoshi Watanabe

Proceedings of the 35th Annual IEEE Conference on Local Computer Networks, 2010

Subtractive Color Process for Lossless Compression of Non-photographed Images.

Yasuyuki Miura, Masato Suzuki, Ryo Morikawa, Shigeyoshi Watanabe

Proceedings of the 2010 International Conference on Image Processing, 2010

2008

A Quantitative Method for Comparing Multi-Agent-Based Simulations in Feature Space.

Ryota Arai, Shigeyoshi Watanabe

Proceedings of the Multi-Agent-Based Simulation IX, International Workshop, 2008

2007

A Case Study of Applying SNA to Analyze CSCL Social Network.

Zuoliang Chen, Shigeyoshi Watanabe

Proceedings of the 7th IEEE International Conference on Advanced Learning Technologies, 2007

Comparison of discriminatory pricing and uniform pricing rules in electricity markets using an agent model with risk consideration.

Guilan Zhi, Shigeyoshi Watanabe

Proceedings of the IEEE Congress on Evolutionary Computation, 2007

2006

Design of a 128-mb SOI DRAM using the floating body cell (FBC).

Takashi Ohsawa, Katsuyuki Fujita, Kosuke Hatsuda, Tomoki Higashi, Tomoaki Shino, Yoshihiro Minami, Hiroomi Nakajima, Mutsuo Morikado, Kazumi Inoh, Takeshi Hamamoto, Shigeyoshi Watanabe, Shuso Fujii, Tohru Furuyama

IEEE J. Solid State Circuits, 2006

A Fuzzy Model for Bidding Behavior of Participants in Electricity Markets.

Guilan Zhi, Shigeyoshi Watanabe

Proceedings of the First International Conference on Innovative Computing, Information and Control (ICICIC 2006), 30 August, 2006

2005

Policy Control in Multiagent System.

Ariuna Damba, Shigeyoshi Watanabe

Proceedings of the IASTED International Conference on Computational Intelligence, 2005

Culture & Motivation: Establishing an International Storytelling Forum.

Zuoliang Chen, Shigeyoshi Watanabe

Proceedings of the Cognition and Exploratory Learning in Digital Age, 2005

MASSE: environment supporting for simulation and analysis of multiagent systems.

Tomomi Takashina, Zhenbo Bi, Ariuna Damba, Guilan Zhi, Kazuhide Tanaka, Hiroki Sayama, Shigeyoshi Watanabe

Proceedings of the 2005 International Symposium on Collaborative Technologies and Systems, 2005

2004

Intelligent control in dynamic system.

Ariuna Damba, Shigeyoshi Watanabe

Proceedings of the 2004 IEEE Conference on Robotics, Automation and Mechatronics, 2004

2002

Individual Level Analysis Using Decision Making Features in Multiagent Based Simulation.

Tomomi Takashina, Kazuhide Tanaka, Shigeyoshi Watanabe

Proceedings of the Intelligent Agents and Multi-Agent Systems, 2002

1998

Noise suppression scheme for gigabit-scale and gigabyte/s data-rate LSI's.

Daisaburo Takashima, Yukihito Oowaki, Shigeyoshi Watanabe, Kazunori Ohuchi

IEEE J. Solid State Circuits, 1998

1994

Standby/active mode logic for sub-1-V operating ULSI memory.

Daisaburo Takashima, Shigeyoshi Watanabe, Hiroalu Nakano, Yukihito Oowaki, Kazunori Ohuchi, Hiroyuki Tango

IEEE J. Solid State Circuits, April, 1994

Open/folded bit-line arrangement for ultra-high-density DRAM's.

Daisaburo Takashima, Shigeyoshi Watanabe, Hiroaki Nakano, Yukihito Oowaki, Kazunori Ohuchi

IEEE J. Solid State Circuits, April, 1994

Offset compensating bit-line sensing scheme for high density DRAM's.

Yohji Watanabe, Nobuo Nakamura, Shigeyoshi Watanabe

IEEE J. Solid State Circuits, January, 1994

1989

A 45-ns 16-Mbit DRAM with triple-well structure.

Syuso Fujii, Masaki Ogihara, Mitsuru Shimizu, Munehiro Yoshida, Kenji Numata, Takahiko Hara, Shigeyoshi Watanabe, Shizuo Sawada, Tomohisa Mizuno, Junpei Kumagai, Susumu Yoshikawa, Sejii Kaki, Yoshikazu Saito, Hideaki Aochi, Takeshi Hamamoto, Koichi Toita

IEEE J. Solid State Circuits, October, 1989

An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode.

Shigeyoshi Watanabe, Yukihito Oowaki, Yasuo Itoh, Koji Sakui, Kenji Numata, Tsuneaki Fuse, Takayuki Kobayashi, Kenji Tsuchida, Masahiko Chiba, Takahiko Hara, Masako Ohta, Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, Takeshi Hamamoto, Kazunori Ohuchi, Fujio Masuoka

IEEE J. Solid State Circuits, June, 1989