Shigeya Tanaka

According to our database1, Shigeya Tanaka authored at least 7 papers between 1988 and 1998.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

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Bibliography

1998
Instruction fetch and dispatch scheme with flag-in-cache/in-IBR.
Syst. Comput. Jpn., 1998

1996
2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor.
IEEE J. Solid State Circuits, 1996

1995
A superscalar RISC processor with pseudo vector processing feature.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

1994
A 120-MHz BiCMOS superscalar RISC processor.
IEEE J. Solid State Circuits, April, 1994

3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor.
IEEE J. Solid State Circuits, March, 1994

1989
A high performance BiCMOS 32-bit microprocessor.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989

1988
1.3- mu m CMOS/bipolar standard cell library for VLSI computers.
IEEE J. Solid State Circuits, April, 1988


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