Shigetoshi Nakatake

According to our database, Shigetoshi Nakatake authored at least 80 papers between 1994 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2020

Implementation of Analog Perceptron as an Essential Element of Configurable Neural Networks.

Chao Geng, Qingji Sun, Shigetoshi Nakatake

Sensors, 2020

A Fully Synthesizable, 0.3V, 10nW Rail-to-rail Dynamic Voltage Comparator.

Xuncheng Zou, Shigetoshi Nakatake

Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

An Analog CMOS Implementation for Multi-layer Perceptron With ReLU Activation.

Chao Geng, Qingji Sun, Shigetoshi Nakatake

Proceedings of the 9th International Conference on Modern Circuits and Systems Technologies, 2020

2019

A Low Voltage Stochastic Flash ADC without Comparator.

Xuncheng Zou, Shigetoshi Nakatake

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019

Density Optimization for Analog Layout Based on Transistor-Array.

Chao Geng, Bo Liu, Shigetoshi Nakatake

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019

On-chip resistance configuration by subthreshold MOSFET-array for ultra weak current sensing.

Xinghuai Zhang, Shigetoshi Nakatake

Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019

An Impedance Measurement of Intravesical Urine Volume Appropriate to Seated Posture.

Ryosuke Sakai, Shigetoshi Nakatake

Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019

2018

Routable and Matched Layout Styles for Analog Module Generation.

Bo Liu, Gong Chen, Bo Yang, Shigetoshi Nakatake

ACM Trans. Design Autom. Electr. Syst., 2018

Analog perceptron circuit with DAC-based multiplier.

Yoritaka Ishiguchi, Daishi Isogai, Takuma Osawa, Shigetoshi Nakatake

Integr., 2018

Low Voltage CMOS Current Mode Reference Circuit without Operational Amplifiers.

Kenya Kondo, Koichi Tanno, Hiroki Tamura, Shigetoshi Nakatake

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

Analog Retargeting Constraint Extraction Based on Fundamental Circuits and Layout Regularity.

Xuncheng Zou, Shigetoshi Nakatake

Proceedings of the 2018 New Generation of CAS, 2018

Hierarchical Floorplanning Based on Analog Structure Tree.

Chao Geng, Shigetoshi Nakatake

Proceedings of the 2018 New Generation of CAS, 2018

On-chip Impedance Evaluation with Auto-calibration based on Auto-balancing Bridge.

Takaaki Shirakawa, Ryosuke Sakai, Shigetoshi Nakatake

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

2017

Analog Characterization Module with Data Converter-Coupled Signal Reconfiguration.

Daishi Isogai, Bo Liu, Yoritaka Ishiguchi, Shigetoshi Nakatake

Proceedings of the New Generation of CAS, 2017

A Perceptron Circuit with DAC-Based Multiplier for Sensor Analog Front-Ends.

Yoritaka Ishiguchi, Daishi Isogai, Takuma Osawa, Shigetoshi Nakatake

Proceedings of the New Generation of CAS, 2017

Explicit layout pattern density controlling based on transistor-array-style.

Chao Geng, Bo Liu, Shigetoshi Nakatake

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Overview of the 2017 CAD contest at ICCAD: Invited paper.

Myung-Chul Kim, Shih-Hsu Huang, Rung-Bin Lin, Shigetoshi Nakatake

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Low Voltage Stochastic Flash ADC with Front-end of Inverter-based Comparative Unit.

Xuncheng Zou, Bo Liu, Shigetoshi Nakatake

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016

DC Characteristics and Variability on 90nm CMOS Transistor Array-Style Analog Layout.

Gong Chen, Toru Fujimura, Qing Dong, Shigetoshi Nakatake, Bo Yang

ACM Trans. Design Autom. Electr. Syst., 2016

Subblock-Level Matching Layout for Analog Block-Pair and Its Layout-Dependent Manufacturability Evaluation.

Takuya Hirata, Ryuta Nishino, Shigetoshi Nakatake, Masaya Shimoyama, Masashi Miyagawa, Ryoichi Miyauchi, Koichi Tanno, Akihiro Yamada

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

A Sensor-Based Data Visualization System for Training Blood Pressure Measurement by Auscultatory Method.

Chooi-Ling Goh, Shigetoshi Nakatake

IEICE Trans. Inf. Syst., 2016

A multi-functional memory unit with PLA-based reconfigurable decoder.

Nobuyuki Yahiro, Bo Liu, Atsushi Nanri, Shigetoshi Nakatake, Yasuhiro Takashima, Gong Chen

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

Routability of twisted common-centroid capacitor array under signal coupling constraints.

Gong Chen, Bo Liu, Shigetoshi Nakatake, Bo Yang

Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

Twin-row-style for MOS analog layout.

Bo Liu, Shigetoshi Nakatake, Bo Yang, Gong Chen

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Overview of the 2016 CAD contest at ICCAD.

Shih-Hsu Huang, Rung-Bin Lin, Myung-Chul Kim, Shigetoshi Nakatake

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2015

Layout Dependent Effect-Aware Leakage Current Reduction and Its Application to Low-Power SAR-ADC.

Gong Chen, Yu Zhang, Qing Dong, Mingyu Li, Shigetoshi Nakatake

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

Low-Power and Low-Variability Programmable Delay Element and Its Application to Post-Silicon Skew Tuning.

Daijiro Murooka, Yu Zhang, Qing Dong, Shigetoshi Nakatake

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Subblock-level matching layout for analog block-pair and its manufacturability evaluation.

Takuya Hirata, Ryuta Nishino, Shigetoshi Nakatake, Masaya Shimoyama, Masashi Miyagawa, Koichi Tanno, Akihiro Yamada

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2013

Analog Circuit Synthesis with Constraint Generation of Layout-Dependent Effects by Geometric Programming.

Yu Zhang, Gong Chen, Bo Yang, Jing Li, Qing Dong, Mingyu Li, Shigetoshi Nakatake

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Structured Analog Circuit and Layout Design with Transistor Array.

Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Performance-driven SRAM macro design with parameterized cell considering layout-dependent effects.

Yu Zhang, Gong Chen, Qing Dong, Mingyu Li, Shigetoshi Nakatake

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

A comparator energy model considering shallow trench isolation stress by geometric programming.

Gong Chen, Yu Zhang, Bo Yang, Qing Dong, Shigetoshi Nakatake

Proceedings of the International Symposium on Quality Electronic Design, 2013

Practicality on placement given by optimality of packing.

Shigetoshi Nakatake

Proceedings of the International Symposium on Physical Design, 2013

A 9-bit 50msps SAR ADC with pre-charge VCM -based double input range algorithm.

Gong Chen, Bo Yang, Yu Zhang, Qing Dong, Shigetoshi Nakatake

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

2012

Layout-Aware Variability Characterization of CMOS Current Sources.

Bo Liu, Bo Yang, Shigetoshi Nakatake

IEICE Trans. Electron., 2012

CMOS op-amp circuit synthesis with geometric programming models for layout-dependent effects.

Yu Zhang, Bo Liu, Bo Yang, Jing Li, Shigetoshi Nakatake

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Transistor channel decomposition for structured analog layout, manufacturability and low-power applications.

Qing Dong, Bo Yang, Gong Chen, Jing Li, Shigetoshi Nakatake

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

A retargeting methodology of nano-watt CMOS reference circuit based on advanced compact MOSFET model.

Gong Chen, Bo Yang, Shigetoshi Nakatake, Zhangcai Huang, Yasuaki Inoue

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011

Layout-aware mismatch modeling for CMOS current sources with D/A converter analysis.

Bo Liu, Qing Dong, Bo Yang, Jing Li, Shigetoshi Nakatake

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Layout-aware variation evaluation of analog circuits and its validity on op-amp designs.

Kota Shinohara, Mihoko Hidaka, Jing Li, Qing Dong, Bo Yang, Shigetoshi Nakatake

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

2010

Regularity-Oriented Analog Placement with Conditional Design Rules.

Shigetoshi Nakatake, Masahiro Kawakita, Takao Ito, Masahiro Kojima, Michiko Kojima, Kenji Izumi, Tadayuki Habasaki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Photomask Data Prioritization Based on VLSI Design Intent and Its Utilization for Mask Manufacturing.

Kokoro Kato, Masakazu Endo, Tadao Inoue, Shigetoshi Nakatake, Masaki Yamabe, Sunao Ishihara

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Post-placement STI well width adjusting by geometric programming for device mobility enhancement in critical path.

Jing Li, Bo Yang, Qing Dong, Shigetoshi Nakatake

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Structured analog circuit design and MOS transistor decomposition for high accuracy applications.

Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Regularity-oriented analog placement with diffusion sharing and well island generation.

Shigetoshi Nakatake, Masahiro Kawakita, Takao Ito, Masahiro Kojima, Michiko Kojima, Kenji Izumi, Tadayuki Habasaki

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

D-A converter based variation analysis for analog layout design.

Bo Liu, Toru Fujimura, Bo Yang, Shigetoshi Nakatake

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

Structured Placement with Topological Regularity Evaluation.

Qing Dong, Shigetoshi Nakatake

IPSJ Trans. Syst. LSI Des. Methodol., 2009

Fast Shape Optimization of Metalization Patterns for Power-MOSFET Based Driver.

Bo Yang, Shigetoshi Nakatake

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Incremental Buffer Insertion and Module Resizing Algorithm Using Geometric Programming.

Qing Dong, Bo Yang, Jing Li, Shigetoshi Nakatake

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

STI stress aware placement optimization based on geometric programming.

Jing Li, Bo Yang, Xiaochuan Hu, Qing Dong, Shigetoshi Nakatake

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

2008

A Finite Element-Domain Decomposition Coupled Resistance Extraction Method with Virtual Terminal Insertion.

Bo Yang, Hiroshi Murata, Shigetoshi Nakatake

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Fast Shape Optimization of Metallization Patterns for DMOS Based Driver.

Bo Yang, Shigetoshi Nakatake, Hiroshi Murata

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Transistor-level programmable MOS analog IC with body biasing.

Toru Fujimura, Shigetoshi Nakatake

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Constraint-free analog placement with topological symmetry structure.

Qing Dong, Shigetoshi Nakatake

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

Block placement to ensure channel routability.

Shigetoshi Nakatake, Zohreh Karimi, Taraneh Taghavi, Majid Sarrafzadeh

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Structured Placement with Topological Regularity Evaluation.

Shigetoshi Nakatake

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

The Oct-Touched Tile: A New Architecture for Shape-Based Routing.

Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Formulating the Empirical Strategies in Module Generation of Analog MOS Layout.

Tan Yan, Shigetoshi Nakatake, Takashi Nojima

Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Adaptive Porting of Analog IPs with Reusable Conservative Properties.

Takashi Nojima, Nobuto Ono, Shigetoshi Nakatake, Toru Fujimura, Koji Okazaki, Yoji Kajitani

Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Multi-SP: A Representation with United Rectangles for Analog Placement and Routing.

Ning Fu, Mitsutoshi Mineshima, Shigetoshi Nakatake

Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Sequence-Pair Based Compaction under Equi-Length Constraint.

Keiji Kida, Takehiko Matsuo, Tetsuya Tashiro, Shigetoshi Nakatake

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2004

A fast algorithm for crosspoint assignment under crosstalk constraints with shielding effects.

Keiji Kida, Xiaoke Zhu, Changwen Zhuang, Yasuhiro Takashima, Shigetoshi Nakatake

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A device-level placement with multi-directional convex clustering.

Takashi Nojima, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Multi-level placement with circuit schema based clustering in analog IC layouts.

Takashi Nojima, Xiaoke Zhu, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Abstraction and optimization of consistent floorplanning with pillar block constraints.

Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

An Incremental Wiring Algorithm for VLSI Layout Design.

Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

2002

Consistent floorplanning with hierarchical superconstraints.

Shigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts.

Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Chip size estimation based on wiring area.

Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001

Consistent floorplanning with super hierarchical constraints.

Shigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani

Proceedings of the 2001 International Symposium on Physical Design, 2001

2000

Partition, Packing and Clock Distribution-A New Paradigm of Physical Design.

Yoji Kajitani, Atsushi Takahashi, Kengo R. Azegami, Shigetoshi Nakatake

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Self-reforming routing for stochastic search in VLSI interconnection layout.

Yukiko Kubo, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani

Proceedings of ASP-DAC 2000, 2000

1998

Module packing based on the BSG-structure and IC layout applications.

Shigetoshi Nakatake, Kunihiro Fujiyoshi, Hiroshi Murata, Yoji Kajitani

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks.

Keishi Sakanushi, Shigetoshi Nakatake, Yoji Kajitani

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications.

Shigetoshi Nakatake, Keishi Sakanushi, Yoji Kajitani, Masahiro Kawakita

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Module Placement on BSG-Structure with Pre-Placed Modules and Rectilinear Modules.

Shigetoshi Nakatake, Masahiro Furuya, Yoji Kajitani

Proceedings of the ASP-DAC '98, 1998

1996

VLSI module placement based on rectangle-packing by the sequence-pair.

Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Module placement on BSG-structure and IC layout applications.

Shigetoshi Nakatake, Kunihiro Fujiyoshi, Hiroshi Murata, Yoji Kajitani

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

1995

Rectangle-packing-based module placement.

Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

1994

Channel-driven global routing with consistent placement (extended abstract).

Shigetoshi Nakatake, Yoji Kajitani

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994