Shigeto Tanaka
According to our database1,
Shigeto Tanaka
authored at least 3 papers
between 2005 and 2007.
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Bibliography
2007
A Digitally Assisted Gain and Offset Error Cancellation Technique for a CMOS Pipelined ADC with a 1.5-bit Bit-Block Architecture.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
2006
A Study to Realize a CMOS Pipelined Current-Mode A-to-D Converter for Video Applications.
IEICE Trans. Electron., 2006
2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005