Shigeto Tanaka

According to our database1, Shigeto Tanaka authored at least 3 papers between 2005 and 2007.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2007
A Digitally Assisted Gain and Offset Error Cancellation Technique for a CMOS Pipelined ADC with a 1.5-bit Bit-Block Architecture.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

2006
A Study to Realize a CMOS Pipelined Current-Mode A-to-D Converter for Video Applications.
IEICE Trans. Electron., 2006

2005
The realization of a mismatch-free and 1.5-bit over-sampling pipelined ADC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005


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