Shigeru Yamashita
Orcid: 0000-0002-2279-4644
According to our database1,
Shigeru Yamashita
authored at least 128 papers
between 1995 and 2025.
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Bibliography
2025
Reducing T-Count in Quantum Circuits Using Alternate Forms of the Relative Phase Toffoli Gate.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2025
2024
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024
Optimization for Gaussian Elimination-Based NNA-Compliant Circuit Synthesis Method by Inserting CN OT Gates.
Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2024
Utilizing Don't-Cares to Minimize CNOTs in Synthesizing NNA Compliant Quantum Circuits.
Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2024
An Efficient Error Correction Method for DMFBs with Node Redundancy Considering Node Levels.
Proceedings of the 21st International SoC Design Conference, 2024
An Efficient Cost Reduction Method By Reusing Intermediate Droplets in MEDA Biochips.
Proceedings of the 21st International SoC Design Conference, 2024
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
Proceedings of the 6th International Symposium on Advanced Technologies and Applications in the Internet of Things, 2024
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024
2023
A Deep Reinforcement Learning Approach to Droplet Routing for Erroneous Digital Microfluidic Biochips.
Sensors, November, 2023
Enhancing VQE Convergence for Optimization Problems with Problem-Specific Parameterized Quantum Circuits.
IEICE Trans. Inf. Syst., November, 2023
A SAT Approach to the Initial Mapping Problem in SWAP Gate Insertion for Commuting Gates.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., November, 2023
Preparing Fluid Samples Under Retention Time Constraints Using Flow-Based Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023
Making General Dilution Graphs Robust to Unbalanced-Split Errors on Digital Microfluidic Biochips.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., February, 2023
An Efficient Method to Decompose and Map MPMCT Gates That Accounts for Qubit Placement.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., February, 2023
Transport-Free Placement of Mixers for Realizing Bioprotocol on Programmable Microfluidic Devices.
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
A Deep Reinforcement Learning-based Routing Algorithm for Unknown Erroneous Cells in DMFBs.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
Using S Gates and Relative Phase Toffoli Gates to Improve T-Count in Quantum Boolean Circuits.
Proceedings of the 53rd IEEE International Symposium on Multiple-Valued Logic, 2023
Optimizing LUT-Based Quantum Circuit Synthesis Using Relative Phase Boolean Operations.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
Proceedings of the International Conference on Electronics, Information, and Communication, 2023
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023
An SMT-Solver-Based Synthesis of NNA-Compliant Quantum Circuits Consisting of CNOT, H and T Gates.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., October, 2022
Proceedings of the Reversible Computation - 14th International Conference, 2022
2021
Fluid-to-cell assignment and fluid loading on programmable microfluidic devices for bioprotocol execution.
Integr., 2021
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021
Proceedings of the 18th International SoC Design Conference, 2021
Design for Restricted-Area and Fast Dilution using Programmable Microfluidic Device based Lab-on-a-Chip.
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021
Proceedings of the IEEE Biomedical Circuits and Systems Conference, BioCAS 2021, 2021
Dynamical Decomposition and Mapping of MPMCT Gates to Nearest Neighbor Architectures.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
Exact Synthesis of Nearest Neighbor Compliant Quantum Circuits in 2-D Architecture and Its Application to Large-Scale Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Efficient Methods to Generate Constant SNs with Considering Trade-Off between Error and Overhead and Its Evaluation.
IEICE Trans. Inf. Syst., 2020
CCF Trans. High Perform. Comput., 2020
Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020
Transport-Free Module Binding for Sample Preparation using Microfluidic Fully Programmable Valve Arrays.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Optimization of Fluid Loading on Programmable Microfluidic Devices for Bio-protocol Execution.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
Design Automation for Dilution of a Fluid Using Programmable Microfluidic Device-Based Biochips.
ACM Trans. Design Autom. Electr. Syst., 2019
Threshold Function Identification by Redundancy Removal and Comprehensive Weight Assignments.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Mapping a Quantum Circuit to 2D Nearest Neighbor Architecture by Changing the Gate Order.
IEICE Trans. Inf. Syst., 2019
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
Reactant Minimization for Multi-Target Sample Preparation on Digital Microfluidic Biochips Using Network Flow Models.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019
Proceedings of the Reversible Computation - 11th International Conference, 2019
Proceedings of the 2019 International SoC Design Conference, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
Quantum Circuit Optimization by Changing the Gate Order for 2D Nearest Neighbor Architectures.
Proceedings of the Reversible Computation - 10th International Conference, 2018
2017
Microfluidic Biochips: Bridging Biochemistry with Computer Science and Engineering (NII Shonan Meeting 2017-1).
NII Shonan Meet. Rep., 2017
A Systematic Methodology for Design and Worst-Case Error Analysis of Approximate Array Multipliers.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
IEICE Trans. Inf. Syst., 2017
2016
A Full-Flexibility-Guaranteed Pin-Count Reduction Design for General-Purpose Digital Microfluidic Biochips.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016
Area/latency optimized early output asynchronous full adders and relative-timed ripple carry adders.
CoRR, 2016
Comput. Complex., 2016
ILP-based Synthesis for Sample Preparation Applications on Digital Microfluidic Biochips.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Design of Microfluidic Biochips: Connecting Algorithms and Foundations of Chip Design to Biochemistry and the Life Sciences.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
A pre-optimization technique to generate initial reversible circuits with low quantum cost.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Effect of LFSR seeding, scrambling and feedback polynomial on stochastic computing accuracy.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
An Optimal Pin-Count Design With Logic Optimization for Digital Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
A general testing method for digital microfluidic biochips under physical constraints.
Proceedings of the 2015 IEEE International Test Conference, 2015
Proceedings of the 20th IEEE European Test Symposium, 2015
2014
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
Proceedings of the Reversible Computation - 6th International Conference, 2014
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
A network-flow-based optimal sample preparation algorithm for digital microfluidic biochips.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
IEICE Trans. Inf. Syst., 2013
On the Error Resiliency of Combinational Logic Cells - Implications for Nano-based Digital Design.
Proceedings of the IEEE 19th Pacific Rim International Symposium on Dependable Computing, 2013
A clique-based approach to find binding and scheduling result in flow-based microfluidic biochips.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
J. Multiple Valued Log. Soft Comput., 2012
Electron. Colloquium Comput. Complex., 2012
Proceedings of the Algorithm Theory - SWAT 2012, 2012
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
Proceedings of the 21st IEEE Asian Test Symposium, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
An efficient conversion of quantum circuits to a linear nearest neighbor architecture.
Quantum Inf. Comput., 2011
Proceedings of the Reversible Computation - Third International Workshop, 2011
An efficient algorithm for constructing a Sequence Binary Decision Diagram representing a set of reversed sequences.
Proceedings of the 2011 IEEE International Conference on Granular Computing, 2011
2010
2009
Synthesis of quantum circuits for d-level systems by using cosine-sine decomposition.
Quantum Inf. Comput., 2009
IEICE Trans. Inf. Syst., 2009
2008
DDMF: An Efficient Decision Diagram Structure for Design Verification of Quantum Circuits under a Practical Restriction.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
Proceedings of the 14th IEEE Pacific Rim International Symposium on Dependable Computing, 2008
Proceedings of the Algorithms and Computation, 19th International Symposium, 2008
Proceedings of the Automata, Languages and Programming, 35th International Colloquium, 2008
Proceedings of 8th IEEE International Conference on Computer and Information Technology, 2008
2007
Theor. Comput. Sci., 2007
IEICE Trans. Inf. Syst., 2007
Proceedings of the Algorithms and Computation, 18th International Symposium, 2007
Proceedings of the Automata, Languages and Programming, 34th International Colloquium, 2007
Proceedings of the IEEE Congress on Evolutionary Computation, 2007
A Hardware SAT Solver Using Non-chronological Backtracking and Clause Recording Without Overheads.
Proceedings of the Reconfigurable Computing: Architectures, 2007
2006
An Efficient and Effective Algorithm for Online Task Placement with I/O Communications in Partially Reconfigurable FPGAs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
Proceedings of the Proceedings 2006 IEEE International Symposium on Information Theory, 2006
Proceedings of the Computing and Combinatorics, 12th Annual International Conference, 2006
Proceedings of the 40th Annual Conference on Information Sciences and Systems, 2006
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
Reconfigurable 1-Bit Processor Array with Reduced Wirng Area.
Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
SPFD-based effective one-to-many rewiring (OMR) for delay reduction of LUT-based FPGA circuits.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004
2003
New Gener. Comput., 2003
New Gener. Comput., 2003
2002
Proceedings of the 39th Design Automation Conference, 2002
2000
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
An efficient framework of using various decomposition methods to synthesize LUT networks and its evaluation.
Proceedings of ASP-DAC 2000, 2000
1999
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999
1998
Restructuring Logic Representations with Easily Detectable Simple Disjunctive Decompositions.
Proceedings of the 1998 Design, 1998
Proceedings of the ASP-DAC '98, 1998
1997
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997
1996
Syst. Comput. Jpn., 1996
Syst. Comput. Jpn., 1996
A new method to express functional permissibilities for LUT based FPGAs and its applications.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996
1995
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995