Shigeru Kikuda

According to our database, Shigeru Kikuda authored at least 4 papers between 1991 and 2005.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2005

Highly Flexible Row and Column Redundancy and Cycle Time Adaptive Read Data Path for Double Data Rate Synchronous Memories.

Kiyohiro Furutani, Takeshi Hamamoto, Takeo Miki, Masaya Nakano, Takashi Kono, Shigeru Kikuda, Yasuhiro Konishi, Tsutomu Yoshihara

IEICE Trans. Electron., 2005

2000

A 0.18-μm 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica.

Shigehiro Kuge, Tetsuo Kato, Kiyohiro Furutani, Shigeru Kikuda, Katsuyoshi Mitsui, Takeshi Hamamoto, Jun Setogawa, Kei Hamade, Yuichiro Komiya, Satoshi Kawasaki, Takashi Kono, Teruhiko Amano, Takashi Kubo, Masaru Haraguchi, Yoshito Nakaoka, Mihoko Akiyama, Yasuhiro Konishi, Hideyuki Ozaki, Tsutomu Yoshihara

IEEE J. Solid State Circuits, 2000

1991

A 45-ns 64-Mb DRAM with a merged match-line test architecture.

Shigeru Mori, Hiroshi Miyamoto, Yoshikazu Morooka, Shigeru Kikuda, Makoto Suwa, Mitsuya Kinoshita, Atsushi Hachisuka, Hideaki Arima, Michihiro Yamada, Tsutomu Yoshihara, Shimpei Kayano

IEEE J. Solid State Circuits, November, 1991

Optimized redundancy selection based on failure-related yield model for 64-Mb DRAM and beyond.

Shigeru Kikuda, Hiroshi Miyamoto, Shigeru Mori, Mitsutaka Niiro, Michihiro Yamada

IEEE J. Solid State Circuits, November, 1991