Shigeo Kuninobu

According to our database, Shigeo Kuninobu authored at least 4 papers between 1987 and 1997.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1997

A Partial Scan Design Method Based on n-Fold Line-up Structures.

Toshinori Hosokawa, Toshihiro Hiraoka, Mitsuyasu Ohta, Michiaki Muraoka, Shigeo Kuninobu

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1994

Accurate Ronding Scheme for the Newton-Raphson Method Using Redundant Binary Representation.

Hideyuki Kabuo, Takashi Taniguchi, Akira Miyoshi, Hitoshi Yamashita, Miki Urano, Hisakazu Edamatsu, Shigeo Kuninobu

IEEE Trans. Computers, 1994

1990

A highly integrated 40-MIPS (peak) 64-b RISC microprocessor.

Jito Miyake, Todhinoti Maeda, Yoshito Nishimichi, Johi Katsura, Takashi Taniguchi, Seihi Yamaguchi, Hisakazu Edamatsu, Shigeru Watari, Yoshiyuko Takagi, Kazuhiko Tsuji, Shigeo Kuninobu, Steve Cox, Douglas Duschatko, Douglas MacGregor

IEEE J. Solid State Circuits, October, 1990

1987

Design of high speed MOS multiplier and divider using redundant binary representation.

Shigeo Kuninobu, Tamotsu Nishiyama, Hisakazu Edamatsu, Takashi Taniguchi, Naofumi Takagi

Proceedings of the 8th IEEE Symposium on Computer Arithmetic, 1987