Shigenobu Komatsu

According to our database, Shigenobu Komatsu authored at least 7 papers between 2002 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2013

A 0.41 µA Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS.

Noriaki Maeda, Shigenobu Komatsu, Masao Morimoto, Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Yasuhisa Shimazaki

IEEE J. Solid State Circuits, 2013

2012

A 0.41µA standby leakage 32Kb embedded SRAM with Low-Voltage resume-standby utilizing all digital current comparator in 28nm HKMG CMOS.

Noriaki Maeda, Shigenobu Komatsu, Masao Morimoto, Yasuhisa Shimazaki

Proceedings of the Symposium on VLSI Circuits, 2012

2010

A Low-Power Wide-Range Clock Synchronizer With Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS.

Masafumi Onouchi, Yusuke Kanno, Makoto Saen, Shigenobu Komatsu, Yoshihiko Yasu, Koichiro Ishibashi

IEEE J. Solid State Circuits, 2010

2009

An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM.

Kiichi Niitsu, Yasuhisa Shimazaki, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Itaru Nonomura, Makoto Saen, Shigenobu Komatsu, Kenichi Osada, Naohiko Irie, Toshihiro Hattori, Atsushi Hasegawa, Tadahiro Kuroda

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation.

Shigenobu Komatsu, Masanao Yamaoka, Masao Morimoto, Noriaki Maeda, Yasuhisa Shimazaki, Kenichi Osada

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2007

In-Situ Measurement of Supply-Noise Maps With Millivolt Accuracy and Nanosecond-Order Time Resolution.

Yusuke Kanno, Yuki Kondoh, Takahiro Irita, Kenji Hirose, Ryo Mori, Yoshihiko Yasu, Shigenobu Komatsu, Hiroyuki Mizuno

IEEE J. Solid State Circuits, 2007

2002

An ultra low power, realtime MPEG2 MP@HL motion estimation processor core with SIMD datapath architecture optimized for gradient descent search algorithm.

Masayuki Miyama, Osamu Tooyama, N. Takamatsu, T. Kodake, K. Nakamura, A. Kato, Junichi Miyakoshi, K. Hashimoto, Shigenobu Komatsu, M. Yagi, Masao Morimoto, Kazuo Taki, Masahiko Yoshimoto

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002