Shichang Zou
According to our database1,
Shichang Zou
authored at least 36 papers
between 2011 and 2023.
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Bibliography
2023
Int. J. Circuit Theory Appl., October, 2023
A highly stable and low-cost 12T radiation hardened SRAM cell design for aerospace application.
Int. J. Circuit Theory Appl., August, 2023
2022
A High-Performance and Low-Cost Single-Event Multiple-Node-Upsets Resilient Latch Design.
IEEE Trans. Very Large Scale Integr. Syst., 2022
2020
IEEE Trans. Circuits Syst. II Express Briefs, 2020
Microelectron. J., 2020
Substrate effect on radiation-induced charge trapping in buried oxide for partially-depleted SOI NMOSFET.
IEICE Electron. Express, 2020
2019
Quadruple Cross-Coupled Latch-Based 10T and 12T SRAM Bit-Cell Designs for Highly Reliable Terrestrial Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Demonstration of improvement of specific on-resistance versus breakdown voltage tradeoff for low-voltage power LDMOS.
Microelectron. J., 2019
IEICE Electron. Express, 2019
Radiation-enhanced channel length modulation induced by trapped charges in buried oxide layer.
IEICE Electron. Express, 2019
Proceedings of the International Conference on IC Design and Technology, 2019
2018
A 280-KBytes Twin-Bit-Cell Embedded NOR Flash Memory With a Novel Sensing Current Protection Enhanced Technique and High-Voltage Generating Systems.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
Investigation and impact of LDD variations on the drain disturb in normally-on SONOS NOR flash device.
Microelectron. Reliab., 2018
IEICE Electron. Express, 2018
IEICE Electron. Express, 2018
IEICE Electron. Express, 2018
Total dose radiation induced changes of the floating body effects in the partially depleted SOI NMOS with ultrathin gate oxide.
IEICE Electron. Express, 2018
2017
Microelectron. Reliab., 2017
Influences of silicon-rich shallow trench isolation on total ionizing dose hardening and gate oxide integrity in a 130 nm partially depleted SOI CMOS technology.
Microelectron. Reliab., 2017
Degradation induced by TID radiation and hot-carrier stress in 130-nm short channel PDSOI NMOSFETs.
Microelectron. Reliab., 2017
Microelectron. J., 2017
A duplex current-reused CMOS LNA with complementary derivative superposition technique.
Int. J. Circuit Theory Appl., 2017
IEICE Electron. Express, 2017
2016
Microelectron. J., 2016
Comparison of single-event transients of T-gate core and IO device in 130 nm partially depleted silicon-on-insulator technology.
IEICE Electron. Express, 2016
2014
A Novel Sourceline Voltage Compensation Circuit and a Wordline Voltage-Generating System for Embedded nor Flash Memory.
IEEE Trans. Circuits Syst. II Express Briefs, 2014
A 1.35-V 16-Mb Twin-Bit-Cell Virtual-Ground-Architecture Embedded Flash Memory With a Sensing Current Protection Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
2013
Bias dependence of TID radiation responses of 0.13 μm partially depleted SOI NMOSFETs.
Microelectron. Reliab., 2013
Microelectron. J., 2013
Proceedings of the 2013 Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC), 2013
2012
Radiation-induced shallow trench isolation leakage in 180-nm flash memory technology.
Microelectron. Reliab., 2012
2011
Hole tunneling from valence band and hot-carrier induced hysteresis effect in 0.13 μm partially depleted silicon-on-insulator n-MOSFETs.
Microelectron. Reliab., 2011
Comparison of TID response in core, input/output and high voltage transistors for flash memory.
Microelectron. Reliab., 2011
Microelectron. Reliab., 2011
Microelectron. J., 2011