Shiann-Rong Kuang

According to our database, Shiann-Rong Kuang authored at least 21 papers between 1993 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

Hardware Implementation of an Automatic Color Equalization Algorithm for Real-time Image Enhancement.

Xiang-Yu Chen, Yu-Hsiang Wang, Yao-Song Zhang, Yen-Jui Chen, Shiann-Rong Kuang

Proceedings of the 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022

2017

Design and implementation of a low-cost guided image filter for underwater image enhancement.

Cheng-Hao Chang, I-Chang Huang, Mu-Fan Lin, Shiann-Rong Kuang

Proceedings of the IEEE Conference on Dependable and Secure Computing, 2017

2016

Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication.

Shiann-Rong Kuang, Kun-Yi Wu, Ren-Yao Lu

IEEE Trans. Very Large Scale Integr. Syst., 2016

An Efficient Radix-4 Scalable Architecture for Montgomery Modular Multiplication.

Shiann-Rong Kuang, Chih-Yuan Liang, Chun-Chi Chen

IEEE Trans. Circuits Syst. II Express Briefs, 2016

2015

An OpenGL ES 2.0 3D graphics SoC with versatile HW/SW development support.

Hsu-Kang Dow, Ching-Hua Huang, Chun-Hung Lai, Kai-Hsiang Tsao, Sheng-Chih Tseng, Kun-Yi Wu, Ting-Hsuan Wu, Ho-Chun Yang, Da-Jing Zhang-Jian, Yun-Nan Chang, Steve Haga, Shen-Fu Hsiao, Ing-Jer Huang, Shiann-Rong Kuang, Chung-Nan Lee

Proceedings of the VLSI Design, Automation and Test, 2015

2014

Efficient architecture and hardware implementation of hybrid fuzzy-Kalman filter for workload prediction.

Shiann-Rong Kuang, Kun-Yi Wu, Bao-Chen Ke, Jia-Huei Yeh, Hao-Yi Jheng

Integr., 2014

2013

Energy-Efficient Multiple-Precision Floating-Point Multiplier for Embedded Applications.

Shiann-Rong Kuang, Kun-Yi Wu, Kee-Khuan Yu

J. Signal Process. Syst., 2013

Energy-Efficient High-Throughput Montgomery Modular Multipliers for RSA Cryptosystems.

Shiann-Rong Kuang, Jiun-Ping Wang, Kai-Cheng Chang, Huan-Wei Hsu

IEEE Trans. Very Large Scale Integr. Syst., 2013

An exact method for estimating maximum errors of multi-mode floating-point iterative booth multiplier.

Kun-Yi Wu, Shiann-Rong Kuang, Kee-Khuan Yu

Int. J. Comput. Sci. Eng., 2013

Multiple-mode floating-point multiply-add fused unit for trading accuracy with power consumption.

Kun-Yi Wu, Chih-Yuan Liang, Kee-Khuan Yu, Shiann-Rong Kuang

Proceedings of the 2013 IEEE/ACIS 12th International Conference on Computer and Information Science, 2013

2011

High-Accuracy Fixed-Width Modified Booth Multipliers for Lossy Applications.

Jiun-Ping Wang, Shiann-Rong Kuang, Shish-Chang Liang

IEEE Trans. Very Large Scale Integr. Syst., 2011

2010

Variable-Latency Floating-Point Multipliers for Low-Power Applications.

Shiann-Rong Kuang, Jiun-Ping Wang, Hong-Yi Huang

IEEE Trans. Very Large Scale Integr. Syst., 2010

Design of Power-Efficient Configurable Booth Multiplier.

Shiann-Rong Kuang, Jiun-Ping Wang

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

2009

Modified Booth Multipliers With a Regular Partial Product Array.

Shiann-Rong Kuang, Jiun-Ping Wang, Cang-Yuan Guo

IEEE Trans. Circuits Syst. II Express Briefs, 2009

2007

Design of power-efficient pipelined truncated multipliers with various output precision.

Shiann-Rong Kuang, Jiun-Ping Wang

IET Comput. Digit. Tech., 2007

Area-Efficient Signed Fixed-Width Multipliers with Low-Error Compensation Circuit.

Jiun-Ping Wang, Shiann-Rong Kuang

Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

2005

Partitioning and Pipelined Scheduling of Embedded System Using Integer Linear Programming.

Shiann-Rong Kuang, Chin-Yang Chen, Ren-Zheng Liao

Proceedings of the 11th International Conference on Parallel and Distributed Systems, 2005

2002

Design of a dynamic pipelined architecture for fuzzy color correction.

Jer-Min Jou, Shiann-Rong Kuang, Yeu-Horng Shiau, Ren-Der Chen

IEEE Trans. Very Large Scale Integr. Syst., 2002

1999

A New Pipelined Architecture for Fuzzy Color Correction.

Jer-Min Jou, Shiann-Rong Kuang, Yeu-Horng Shiau

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1994

Multiport Memory Based Data Path Allocation Focusing on Interconnection Optimization.

Jer-Min Jou, Ren-Der Chen, Shiann-Rong Kuang

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993

Library-Adaptively Integrated Data Path Synthesis for DSP Systems.

Jer-Min Jou, Shiann-Rong Kuang

Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993