Shi-Ce Ni

According to our database, Shi-Ce Ni authored at least 12 papers between 2010 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2019

A Novel Memory-Scheduling Strategy for Large Convolutional Neural Network on Memory-Limited Devices.

Shijie Li, Xiaolong Shen, Yong Dou, Shi-Ce Ni, Jinwei Xu, Ke Yang, Qiang Wang, Xin Niu

Comput. Intell. Neurosci., 2019

A Novel Text Classification Approach Based on Word2vec and TextRank Keyword Extraction.

Shouyou Song, Zhongru Wang, Shuai Xu, Shi-Ce Ni, Jia Xiao

Proceedings of the Fourth IEEE International Conference on Data Science in Cyberspace, 2019

2014

Design and Implement of High Performance Crypto Coprocessor.

Shi-Ce Ni, Yong Dou, Kai Chen, Jie Zhou

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Rapid Acquisition Assisted by Navigation Data for Inter-Satellite Links of Navigation Constellation.

Xian-Bin Li, Yue-Ke Wang, Jian-Yun Chen, Shi-Ce Ni

IEICE Trans. Commun., 2014

An Efficient Parallel SOVA-Based Turbo Decoder for Software Defined Radio on GPU.

Rongchun Li, Yong Dou, Jiaqing Xu, Xin Niu, Shi-Ce Ni

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Parallel graph traversal for FPGA.

Shi-Ce Ni, Yong Dou, Dan Zou, Rongchun Li, Qiang Wang

IEICE Electron. Express, 2014

A Novel Design of Flexible Crypto Coprocessor and Its Application.

Shi-Ce Ni, Yong Dou, Kai Chen, Lin Deng

Proceedings of the Advanced Computer Architecture - 10th Annual Conference, 2014

2013

High performance sparse matrix-vector multiplication on FPGA.

Dan Zou, Yong Dou, Song Guo, Shi-Ce Ni

IEICE Electron. Express, 2013

Reconfigurable pseudo-NMOS-like logic with hybrid MOS and single-electron transistors.

Xiaobao Chen, Zuocheng Xing, Bingcai Sui, Shi-Ce Ni

IEICE Electron. Express, 2013

Design and Implementation of Novel Flexible Crypto Coprocessor and Its Application in Security Protocol.

Shi-Ce Ni, Yong Dou, Kai Chen, Lin Deng

Proceedings of the Computer Engineering and Technology - 17th CCF Conference, 2013

2012

Design and Implementation of the Parameterized Multi-Standard High-Throughput Radix-4 Viterbi Decoder on FPGA.

Rongchun Li, Yong Dou, Yuanwu Lei, Shi-Ce Ni, Song Guo

IEICE Trans. Commun., 2012

2010

A Unified Co-Processor Architecture for Matrix Decomposition.

Yong Dou, Jie Zhou, Guiming Wu, Jingfei Jiang, Yuanwu Lei, Shi-Ce Ni

J. Comput. Sci. Technol., 2010