Sheyang Ning
Orcid: 0000-0003-0810-187X
According to our database1,
Sheyang Ning
authored at least 9 papers
between 2014 and 2020.
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Bibliography
2020
Improving Resistive RAM Hard and Soft Decision Correctable BERs by Using Improved-LLR and Reset-Check-Reverse-Flag Concatenating LDPC Code.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
2018
Advanced Bit Flip Concatenates BCH Code Demonstrates 0.93% Correctable BER and Faster Decoding on (36 864, 32 768) Emerging Memories.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
2016
Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory.
IEEE J. Solid State Circuits, 2016
Adaptive Comparator Bias-Current Control of 0.6 V Input Boost Converter for ReRAM Program Voltages in Low Power Embedded Applications.
IEEE J. Solid State Circuits, 2016
Variation of SCM/NAND Flash Hybrid SSD Performance, Reliability and Cost by Using Different SSD Configurations and Error Correction Strengths.
IEICE Trans. Electron., 2016
2015
Design Methodology for Highly Reliable, High Performance ReRAM and 3-Bit/Cell MLC NAND Flash Solid-State Storage.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
0.6 V operation, 26% smaller voltage ripple, 9% energy efficient boost converter with adaptively optimized comparator bias-current for ReRAM program in low power IoT embedded applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
Comprehensive comparison of 3D-TSV integrated solid-state drives (SSDs) with storage class memory and NAND flash memory.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015
2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014