Shervin Vakili
Orcid: 0000-0002-4791-9298
According to our database1,
Shervin Vakili
authored at least 20 papers
between 2010 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
IEEE Embed. Syst. Lett., June, 2024
A Cost-Effective Baugh-Wooley Approximate Multiplier for FPGA-based Machine Learning Computing.
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024
2023
CoRR, 2023
A Cost-Effective FPGA-Based Approximate Multiplier for Machine Learning Acceleration.
Proceedings of the 14th IEEE International Symposium on Parallel Architectures, 2023
DSCAM+: Latency-Guaranteed FPGA-Based Content Addressable Memory for SDN-Enabled Forwarding Plane.
Proceedings of the IEEE International Conference on High Performance Computing & Communications, 2023
2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
2020
Heterogeneous Distributed SRAM Configuration for Energy-Efficient Deep CNN Accelerators.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020
An Energy-Efficient Accelerator Architecture with Serial Accumulation Dataflow for Deep CNNs.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020
2018
Enhanced Bloom filter utilisation scheme for string matching using a splitting approach.
IET Commun., 2018
Power Reduction in CNN Pooling Layers with a Preliminary Partial Computation Strategy.
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018
2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
IET Comput. Digit. Tech., 2016
Memory-Efficient String Matching for Intrusion Detection Systems using a High-Precision Pattern Grouping Algorithm.
Proceedings of the 2016 Symposium on Architectures for Networking and Communications Systems, 2016
2015
Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015
2013
Enhanced Precision Analysis for Accuracy-Aware Bit-Width Optimization Using Affine Arithmetic.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
Customised soft processor design: a compromise between architecture description languages and parameterisable processors.
IET Comput. Digit. Tech., 2013
Proceedings of the IEEE International Conference on Acoustics, 2013
2011
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
2010
Evolvable multi-processor: A novel MPSoC architecture with evolvable task decomposition and scheduling.
IET Comput. Digit. Tech., 2010
Parallel scalable hardware implementation of asynchronous discrete particle swarm optimization.
Eng. Appl. Artif. Intell., 2010