Shervin Vakili

Amirhossein Zarei

IEEE Embed. Syst. Lett., June, 2024

HENNC: Hardware Engine for Artificial Neural Network-based Chaotic Oscillators.

[BibT_eX]

[DOI]

Mobin Vaziri

M. Mehdi Rahimifar

CoRR, 2024

A Cost-Effective Baugh-Wooley Approximate Multiplier for FPGA-based Machine Learning Computing.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

2023

Fast and Low-Cost Approximate Multiplier for FPGAs using Dynamic Reconfiguration.

[BibT_eX]

[DOI]

Mobin Vaziri

Amirhossein Zarei

CoRR, 2023

A Cost-Effective FPGA-Based Approximate Multiplier for Machine Learning Acceleration.

[BibT_eX]

[DOI]

Anees Rehman

Proceedings of the 14th IEEE International Symposium on Parallel Architectures, 2023

DSCAM+: Latency-Guaranteed FPGA-Based Content Addressable Memory for SDN-Enabled Forwarding Plane.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on High Performance Computing & Communications, 2023

2021

CARLA: A Convolution Accelerator With a Reconfigurable and Low-Energy Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2020

Heterogeneous Distributed SRAM Configuration for Energy-Efficient Deep CNN Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020

An Energy-Efficient Accelerator Architecture with Serial Accumulation Dataflow for Deep CNNs.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020

2018

Enhanced Bloom filter utilisation scheme for string matching using a splitting approach.

[BibT_eX]

[DOI]

Naraig Manjikian

IET Commun., 2018

Power Reduction in CNN Pooling Layers with a Preliminary Partial Computation Strategy.

[BibT_eX]

[DOI]

Warren J. Gross

Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

2017

Scalable memory-less architecture for string matching with FPGAs.

[BibT_eX]

[DOI]

Ideh Sarbishei

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016

Accuracy-aware processor customisation for fixed-point arithmetic.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2016

Memory-Efficient String Matching for Intrusion Detection Systems using a High-Precision Pattern Grouping Algorithm.

[BibT_eX]

[DOI]

Bochra Boughzala

Proceedings of the 2016 Symposium on Architectures for Networking and Communications Systems, 2016

2015

Designing customized microprocessors for fixed-point computation.

[BibT_eX]

[DOI]

Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015

2013

Enhanced Precision Analysis for Accuracy-Aware Bit-Width Optimization Using Affine Arithmetic.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Customised soft processor design: a compromise between architecture description languages and parameterisable processors.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2013

Finite-precision error modeling using affine arithmetic.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2013

2011

Customized embedded processor design for global photographic tone mapping.

[BibT_eX]

[DOI]

Diana Carolina Gil

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

2010

Evolvable multi-processor: A novel MPSoC architecture with evolvable task decomposition and scheduling.

[BibT_eX]

[DOI]