Shervin Sharifi

According to our database1, Shervin Sharifi authored at least 17 papers between 2003 and 2013.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2013
PROMETHEUS: A Proactive Method for Thermal Management of Heterogeneous MPSoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

2012
TempoMP: Integrated prediction and management of temperature in heterogeneous MPSoCs.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Accurate temperature sensing and efficient dynamic thermal management in MPSoCs.
PhD thesis, 2011

Distributed thermal management for embedded heterogeneous MPSoCs with dedicated hardware accelerators.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Temperature-Aware Scheduling for Embedded Heterogeneous MPSoCs with Special Purpose IP Cores.
Proceedings of 20th International Conference on Computer Communications and Networks, 2011

2010
Accurate Direct and Indirect On-Chip Temperature Sensing for Efficient Dynamic Thermal Management.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Package-Aware Scheduling of embedded workloads for temperature and Energy management on heterogeneous MPSoCs.
Proceedings of the 28th International Conference on Computer Design, 2010

GentleCool: Cooling aware proactive workload scheduling in multi-machine systems.
Proceedings of the Design, Automation and Test in Europe, 2010

Hybrid dynamic energy and thermal management in heterogeneous embedded multiprocessor SoCs.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2008
A Selective Trigger Scan Architecture for VLSI Testing.
IEEE Trans. Computers, 2008

Accurate Temperature Estimation for Efficient Thermal Management.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

An analytical model for the upper bound on temperature differences on a chip.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2006
Scan-Based Structure with Reduced Static and Dynamic Power Consumption.
J. Low Power Electron., 2006

2005
Real-time image compression based on wavelet vector quantization, algorithm and VLSI architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Simultaneous Reduction of Dynamic and Static Power in Scan Structures.
Proceedings of the 2005 Design, 2005

2003
Selective Trigger Scan Architecture for Reducing Power, Time and Data Volume in SoC Testing.
Proceedings of the IFIP VLSI-SoC 2003, 2003

Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003


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