Sherif A. Tawfik
According to our database1,
Sherif A. Tawfik
authored at least 24 papers
between 2006 and 2011.
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Bibliography
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
2010
Dual Supply Voltages and Dual Clock Frequencies for Lower Clock Power and Suppressed Temperature-Gradient-Induced Clock Skew.
IEEE Trans. Very Large Scale Integr. Syst., 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
Robust FinFET Memory Circuits with P-Type Data Access Transistors for Higher Integration Density and Reduced Leakage Power.
J. Low Power Electron., 2009
2008
Clock Distribution Networks with Gradual Signal Transition Time Relaxation for Reduced Power Consumption.
J. Circuits Syst. Comput., 2008
Compact FinFET Memory Circuits with P-Type Data Access Transistors for Low Leakage and Robust Operation.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Characterization of New Static Independent-Gate-Biased FinFET Latches and Flip-Flops under Process Variations.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Statistical Data Stability and Leakage Evaluation of FinFET SRAM Cells with Dynamic Threshold Voltage Tuning under Process Parameter Fluctuations.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Work-function engineering for reduced power and higher integration density: An alternative to sizing for stability in FinFET memory circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Asymmetric dual-gate multi-fin keeper bias options and optimization for low power and robust FinFET domino logic.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
Multi-Vth FinFET sequential circuits with independent-gate bias and work-function engineering for reduced power consumption.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2007
Proceedings of the 2007 IEEE International SOC Conference, 2007
An independent-gate FinFET SRAM cell for high data stability and enhanced integration density.
Proceedings of the 2007 IEEE International SOC Conference, 2007
Dual-V_DD Clock Distribution for Low Power and Minimum Temperature Fluctuations Induced Skew.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distribution.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Buffer Insertion and Sizing in Clock Distribution Networks with Gradual Transition Time Relaxation for Reduced Power Consumption.
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Low Power and Stable FinFET SRAM with Static Independent Gate Bias for Enhanced Integration Density.
Proceedings of the 14th IEEE International Conference on Electronics, 2007
2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006