Sherief Reda

Ann. Oper. Res., August, 2024

MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMs.

[BibT_eX]

[DOI]

Manar Abdelatty

CoRR, 2024

HDLCopilot: Hardware Design Library Querying with Natural Language.

[BibT_eX]

[DOI]

Manar Abdelatty

CoRR, 2024

Analyzing the Impact of Data Selection and Fine-Tuning on Economic and Political Biases in LLMs.

[BibT_eX]

[DOI]

Ahmed Agiza

Mohamed Mostagir

CoRR, 2024

torchmSAT: A GPU-Accelerated Approximation To The Maximum Satisfiability Problem.

[BibT_eX]

[DOI]

CoRR, 2024

PikeLPN: Mitigating Overlooked Inefficiencies of Low-Precision Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2024

MTLoRA: A Low-Rank Adaptation Approach for Efficient Multi-Task Learning.

[BibT_eX]

[DOI]

Ahmed Agiza

Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2024

FairCIM: Fair Interference Mitigation by DNN Switching for Latency-Sensitive Inference Jobs.

[BibT_eX]

[DOI]

Tian Guo

Proceedings of the IEEE International Conference on Autonomic Computing and Self-Organizing Systems, 2024

MediatorDNN: Contention Mitigation for Co-Located DNN Inference Jobs.

[BibT_eX]

[DOI]

Tian Guo

Proceedings of the 17th IEEE International Conference on Cloud Computing, 2024

2023

Throughput Maximization of DNN Inference: Batching or Multi-Tenancy?

[BibT_eX]

[DOI]

Masoumeh Ebrahimi

CoRR, 2023

WeNet: Configurable Neural Network with Dynamic Weight-Enabling for Efficient Inference.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

GraPhSyM: Graph Physical Synthesis Model.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

AdaMTL: Adaptive Input-dependent Inference for Efficient Multi-Task Learning.

[BibT_eX]

[DOI]

Ahmed Agiza

Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2023

Microscale 3-D Capacitance Tomography with a CMOS Sensor Array.

[BibT_eX]

[DOI]

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2023

RUCA: RUntime Configurable Approximate Circuits with Self-Correcting Capability.

[BibT_eX]

[DOI]

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

Coordinated Batching and DVFS for DNN Inference on GPU Accelerators.

[BibT_eX]

[DOI]

Masoumeh Ebrahimi

IEEE Trans. Parallel Distributed Syst., 2022

PACT: An Extensible Parallel Thermal Simulator for Emerging Integration and Cooling Technologies.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Approximate Logic Synthesis Using Boolean Matrix Factorization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Characterizing and Optimizing EDA Flows for the Cloud.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

CasCon: Cascaded Thermal and Electrical Current Throttling for Mobile Devices.

[BibT_eX]

[DOI]

Sofiane Chetoui

IEEE Embed. Syst. Lett., 2022

ISLPED 2021: The 25th Anniversary!

[BibT_eX]

[DOI]

Yiran Chen

IEEE Des. Test, 2022

Alternating Blind Identification of Power Sources for Mobile SoCs.

[BibT_eX]

[DOI]

Proceedings of the ICPE '22: ACM/SPEC International Conference on Performance Engineering, Bejing, China, April 9, 2022

ARBench: Augmented Reality Benchmark For Mobile Devices.

[BibT_eX]

[DOI]

Proceedings of the International IEEE Symposium on Performance Analysis of Systems and Software, 2022

2021

Guest Editors' Introduction: The Resurgence of Open- Source EDA Technology.

[BibT_eX]

[DOI]

Pierre-Emmanuel Gaillardon

Leon Stok

IEEE Des. Test, 2021

BitTrain: Sparse Bitmap Compression for Memory-Efficient Training on the Edge.

[BibT_eX]

[DOI]

CoRR, 2021

BayesTuner: Leveraging Bayesian Optimization For DNN Inference Configuration Selection.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2021

Sparse Bitmap Compression for Memory-Efficient Training on the Edge.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE/ACM Symposium on Edge Computing, 2021

AdaCon: Adaptive Context-Aware Object Detection for Resource-Constrained Embedded Devices.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Workload- and User-aware Battery Lifetime Management for Mobile SoCs.

[BibT_eX]

[DOI]

Sofiane Chetoui

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

BatchSizer: Power-Performance Trade-off for DNN Inference.

[BibT_eX]

[DOI]

Masoumeh Ebrahimi

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

LoCool: Fighting Hot Spots Locally for Improving System Energy Efficiency.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

PowerCoord: Power capping coordination for multi-CPU/GPU servers using reinforcement learning.

[BibT_eX]

[DOI]

Chao Jing

Sustain. Comput. Informatics Syst., 2020

Approximate Logic Synthesis: A Survey.

[BibT_eX]

[DOI]

Ilaria Scarabottolo

Giovanni Ansaloni

George A. Constantinides

Laura Pozzi

Proc. IEEE, 2020

A Resource-Efficient Embedded Iris Recognition System Using Fully Convolutional Networks.

[BibT_eX]

[DOI]

Heng Zhao

ACM J. Emerg. Technol. Comput. Syst., 2020

Coordinated Self-Tuning Thermal Management Controller for Mobile Devices.

[BibT_eX]

[DOI]

Sofiane Chetoui

IEEE Des. Test, 2020

Dual-precision fixed-point arithmetic for low-power ray-triangle intersections.

[BibT_eX]

[DOI]

Comput. Graph., 2020

Simultaneous Estimation of Temperature and Voltage from Digital Delay Diversity.

[BibT_eX]

[DOI]

Xiaoyu Lian

Jacob K. Rosenstein

Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

Low Power Current-Mode Relaxation Oscillators for Temperature and Supply Voltage Monitoring.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: Design Trends, 2020

Temperature and Supply Voltage Monitoring with Current-mode Relaxation Oscillators.

[BibT_eX]

[DOI]

Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

Overview of the OpenROAD Digital Design Flow from RTL to GDS.

[BibT_eX]

[DOI]

Proceedings of the 2020 International Symposium on VLSI Design, Automation and Test, 2020

A Learning-Based Thermal Simulation Framework for Emerging Two-Phase Cooling Technologies.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

AdaSense: Adaptive Low-Power Sensing and Activity Recognition for Wearable Devices.

[BibT_eX]

[DOI]

Jon Nelson

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

ApproxDNN: Incentivizing DNN Approximation in Cloud.

[BibT_eX]

[DOI]

Lena Mashayekhy

Proceedings of the 20th IEEE/ACM International Symposium on Cluster, 2020

DRiLLS: Deep Reinforcement Learning for Logic Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019

Automated High-Level Generation of Low-Power Approximate Computing Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2019

Principles of Information Storage in Small-Molecule Mixtures.

[BibT_eX]

[DOI]

Christopher E. Arcadia

CoRR, 2019

Coordinated DVFS and Precision Control for Deep Neural Networks.

[BibT_eX]

[DOI]

Hassan Hafez-Kolahi

IEEE Comput. Archit. Lett., 2019

Modeling and Optimization of Chip Cooling with Two-Phase Vapor Chambers.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

Generalized Matrix Factorization Techniques for Approximate Logic Synthesis.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Lightweight Deep Neural Network Accelerators Using Approximate SW/HW Techniques.

[BibT_eX]

[DOI]

Proceedings of the Approximate Circuits, Methodologies and CAD., 2019

Approximate Computing for Iris Recognition Systems.

[BibT_eX]

[DOI]

Proceedings of the Approximate Circuits, Methodologies and CAD., 2019

Approximate Logic Synthesis Using Boolean Matrix Factorization.

[BibT_eX]

[DOI]

Proceedings of the Approximate Circuits, Methodologies and CAD., 2019

Approximate Multipliers and Dividers Using Dynamic Bit Selection.

[BibT_eX]

[DOI]

Proceedings of the Approximate Circuits, Methodologies and CAD., 2019

2018

Scale-Out vs Scale-Up: A Study of ARM-based SoCs on Server-Class Workloads.

[BibT_eX]

[DOI]

ACM Trans. Model. Perform. Evaluation Comput. Syst., 2018

Implications of Integrated CPU-GPU Processors on Thermal and Power Management Techniques.

[BibT_eX]

[DOI]

CoRR, 2018

Flexible Deep Neural Network Processing.

[BibT_eX]

[DOI]

CoRR, 2018

Computing with Chemicals: Perceptrons Using Mixtures of Small Molecules.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Symposium on Information Theory, 2018

Parallelized Linear Classification with Volumetric Chemical Perceptrons.

[BibT_eX]

[DOI]

Christopher E. Arcadia

Proceedings of the 2018 IEEE International Conference on Rebooting Computing, 2018

Understanding the Sources of Power Consumption in Mobile SoCs.

[BibT_eX]

[DOI]

Proceedings of the Ninth International Green and Sustainable Computing Conference, 2018

PowerCoord: A Coordinated Power Capping Controller for Multi-CPU/GPU Servers.

[BibT_eX]

[DOI]

Chao Jing

Proceedings of the Ninth International Green and Sustainable Computing Conference, 2018

QoR-aware power capping for approximate big data processing.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Approximate computing for biometrie security systems: A case study on iris scanning.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

BLASYS: approximate logic synthesis using boolean matrix factorization.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

Scheduling on CPU + GPU Processors Under Dynamic Conditions.

[BibT_eX]

[DOI]

J. Low Power Electron., 2017

CARB: A C-State Power Management Arbiter for Latency-Critical Workloads.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2017

CloudV: A cloud-based educational digital design environment.

[BibT_eX]

[DOI]

Mohamed Shalan

Proceedings of the 2017 IEEE International Conference on Microelectronic Systems Education, 2017

LACore: A Supercomputing-Like Linear Algebra Accelerator for SoC-Based Designs.

[BibT_eX]

[DOI]

Samuel Steffl

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Fast Decentralized Power Capping for Server Clusters.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

Blind identification of power sources in processors.

[BibT_eX]

[DOI]

Adel Belouchrani

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Understanding the impact of precision quantization on the accuracy and energy of neural networks.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Hardware-Software Codesign of Accurate, Multiplier-free Deep Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

Understanding the Role of GPGPU-Accelerated SoC-Based ARM Clusters.

[BibT_eX]

[DOI]

Tyler Fox

Proceedings of the 2017 IEEE International Conference on Cluster Computing, 2017

2016

Workload-Aware Power Gating Design and Run-Time Management for Massively Parallel GPGPUs.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Power-aware characterization and mapping of workloads on CPU-GPU processors.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Symposium on Workload Characterization, 2016

Hardware acceleration of feature detection and description algorithms on low-power embedded platforms.

[BibT_eX]

[DOI]

Onur Ulusel

Christopher B. Picardo

Christopher B. Harris

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Scheduling Challenges and Opportunities in Integrated CPU+GPU Processors.

[BibT_eX]

[DOI]

Proceedings of the 14th ACM/IEEE Symposium on Embedded Systems for Real-Time Multimedia, 2016

A low-power dynamic divider for approximate applications.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

Runtime configurable deep neural networks for energy-accuracy trade-off.

[BibT_eX]

[DOI]

Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

Creating Soft Heterogeneity in Clusters Through Firmware Re-configuration.

[BibT_eX]

[DOI]

Mohammed Shoaib

Proceedings of the IEEE/ACM 16th International Symposium on Cluster, 2016

DiBA: Distributed Power Budget Allocation for Large-Scale Computing Clusters.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM 16th International Symposium on Cluster, 2016

2015

Power Budgeting Techniques for Data Centers.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2015

Making sense of thermoelectrics for processor thermal management and energy harvesting.

[BibT_eX]

[DOI]

Sriram Jayakumar

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

How Good Are Low-Power 64-Bit SoCs for Server-Class Workloads?

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Workload Characterization, 2015

DRUM: A Dynamic Range Unbiased Multiplier for Approximate Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2014

Fast Design Exploration for Performance, Power and Accuracy Tradeoffs in FPGA-Based Accelerators.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2014

Novel Techniques for High-Sensitivity Hardware Trojan Detection Using Thermal and Power Maps.

[BibT_eX]

[DOI]

Kangqiao Hu

Farinaz Koushanfar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Thermal-aware layout planning for heterogeneous datacenters.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2014

ABACUS: A technique for automated behavioral synthesis of approximate computing circuits.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Power Mapping of Integrated Circuits Using AC-Based Thermography.

[BibT_eX]

[DOI]

Gary L. Woods

IEEE Trans. Very Large Scale Integr. Syst., 2013

Post-silicon power mapping techniques for integrated circuits.

[BibT_eX]

[DOI]

Stefan Angelevski

Integr., 2013

vCap: Adaptive power capping for virtualized servers.

[BibT_eX]

[DOI]

Can Hankendi

Ayse K. Coskun

Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Power mapping and modeling of multi-core processors.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Mitigating dark-silicon problems using superlattice-based thermoelectric coolers.

[BibT_eX]

[DOI]

Francesco Paterna

Proceedings of the Design, Automation and Test in Europe, 2013

High-sensitivity hardware trojan detection using multimodal characterization.

[BibT_eX]

[DOI]

Kangqiao Hu

Farinaz Koushanfar

Proceedings of the Design, Automation and Test in Europe, 2013

Techniques for energy-efficient power budgeting in data centers.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

High-throughput TSV testing and characterization for 3D integration using thermal mapping.

[BibT_eX]

[DOI]

Gary L. Woods

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012

Thermal prediction and adaptive control through workload phase detection.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2012

Adaptive Power Capping for Servers with Multithreaded Workloads.

[BibT_eX]

[DOI]

Ayse K. Coskun

IEEE Micro, 2012

Power Modeling and Characterization of Computing Devices: A Survey.

[BibT_eX]

[DOI]

Found. Trends Electron. Des. Autom., 2012

Temperature-aware computing: Achievements and remaining challenges.

[BibT_eX]

[DOI]

Dhireesha Kudithipudi

Ayse K. Coskun

Qinru Qiu

Proceedings of the 2012 International Green Computing Conference, 2012

Fast Multi-Objective Algorithmic Design Co-Exploration for FPGA-based Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

2011

Improved Thermal Tracking for Processors Using Hard and Soft Sensor Allocation Techniques.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2011

Thermal and Power Characterization of Real Computing Devices.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

Pack & Cap: adaptive DVFS and thread packing under power caps.

[BibT_eX]

[DOI]

Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

Identifying the optimal energy-efficient operating points of parallel workloads.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Thermal and power characterization of field-programmable gate arrays.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

Improved post-silicon power modeling using AC lock-in techniques.

[BibT_eX]

[DOI]

Gary L. Woods

Proceedings of the 48th Design Automation Conference, 2011

2010

Fast, accurate a priori routing delay estimation.

[BibT_eX]

[DOI]

Jinhai Qiu

Soha Hassoun

Proceedings of the International Workshop on System Level Interconnect Prediction Workshop, 2010

Post-silicon power characterization using thermal infrared emissions.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Thermal monitoring of real processors: techniques for sensor allocation and full characterization.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

Consistent runtime thermal prediction and control through workload phase detection.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

Early estimation of TSV area for power delivery in 3-D integrated circuits.

[BibT_eX]

[DOI]

Nauman H. Khan

Soha Hassoun

Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009

Maximizing the Functional Yield of Wafer-to-Wafer 3-D Integration.

[BibT_eX]

[DOI]

Gregory Smith

Larry Smith

IEEE Trans. Very Large Scale Integr. Syst., 2009

Using circuit structural analysis techniques for networks in systems biology.

[BibT_eX]

[DOI]

Proceedings of the 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), 2009

Reducing the leakage and timing variability of 2D ICcs using 3D ICs.

[BibT_eX]

[DOI]

Aung Si

Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Central vs. distributed dynamic thermal management for multi-core processors: which one is better?

[BibT_eX]

[DOI]

Michael Kadin

Augustus K. Uht

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

High-performance, cost-effective heterogeneous 3D FPGA architectures.

[BibT_eX]

[DOI]

Roto Le

Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

Analyzing the impact of process variations on parametric measurements: Novel models and applications.

[BibT_eX]

[DOI]

Sani R. Nassif

Proceedings of the Design, Automation and Test in Europe, 2009

Spectral techniques for high-resolution thermal characterization with limited sensor data.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

2008

Parametric yield management for 3D ICs: Models and strategies for improvement.

[BibT_eX]

[DOI]

Cesare Ferri

ACM J. Emerg. Technol. Comput. Syst., 2008

Frequency planning for multi-core processors under thermal constraints.

[BibT_eX]

[DOI]

Michael Kadin

Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

Frequency and voltage planning for multi-core processors under thermal constraints.

[BibT_eX]

[DOI]

Michael Kadin

Proceedings of the 26th International Conference on Computer Design, 2008

Within-die process variations: How accurately can they be statistically modeled?

[BibT_eX]

[DOI]

Brendan Hargreaves

Henrik Hult

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

On-Line Adjustable Buffering for Runtime Power Reduction.

[BibT_eX]

[DOI]

Puneet Sharma

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Hardware libraries: An architecture for economic acceleration in soft multi-core environments.

[BibT_eX]

[DOI]

David Meisner

Proceedings of the 25th International Conference on Computer Design, 2007

Strategies for improving the parametric yield and profits of 3D ICs.

[BibT_eX]

[DOI]

Cesare Ferri

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

APlace: A High Quality, Large-Scale Analytical Placer.

[BibT_eX]

[DOI]

Qinke Wang

Proceedings of the Modern Circuit Placement, Best Practices and Results, 2007

2006

A Fast Hierarchical Quadratic Placement Algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Zero-Change Netlist Transformations: A New Technique for Placement Benchmarking.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Wirelength minimization for min-cut placements via placement feedback.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

New and improved BIST diagnosis methods from combinatorial Group testing theory.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Computer-Aided Optimization of DNA Array Design and Manufacturing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

A tale of two nets: studies of wirelength progression in physical design.

[BibT_eX]

[DOI]

Proceedings of the Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), 2006

Effective linear programming based placement methods.

[BibT_eX]

[DOI]

Amit Chowdhary

Proceedings of the 2006 International Symposium on Physical Design, 2006

2005

APlace: a general analytic placement framework.

[BibT_eX]

[DOI]

Qinke Wang

Proceedings of the 2005 International Symposium on Physical Design, 2005

Evaluation of placer suboptimality via zero-change netlist transformations.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Symposium on Physical Design, 2005

A semi-persistent clustering technique for VLSI circuit placement.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Symposium on Physical Design, 2005

Architecture and details of a high quality, large-scale analytical placer.

[BibT_eX]

[DOI]

Qinke Wang

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Intrinsic shortest path length: a new, accurate a priori wirelength estimator.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Power-aware placement.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

2004

Match twice and stitch: a new TSP tour construction heuristic.

[BibT_eX]

[DOI]

Oper. Res. Lett., 2004

Scalable Heuristics for Design of DNA Probe Arrays.

[BibT_eX]

[DOI]

J. Comput. Biol., 2004

On legalization of row-based placements.

[BibT_eX]

[DOI]

Igor L. Markov

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Boosting: Min-Cut Placement with Improved Signal Delay.

[BibT_eX]

[DOI]

Igor L. Markov

Proceedings of the 2004 Design, 2004

Placement feedback: a concept and method for better min-cut placements.

[BibT_eX]

[DOI]

Proceedings of the 41th Design Automation Conference, 2004

Combinatorial group testing methods for the BIST diagnosis problem.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

Engineering a scalable placement heuristic for DNA probe arrays.

[BibT_eX]

[DOI]

Proceedings of the Sventh Annual International Conference on Computational Biology, 2003

Design Flow Enhancements for DNA Arrays.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Evaluation of Placement Techniques for DNA Probe Array Layout.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

2002

Border Length Minimization in DNA Array Design.

[BibT_eX]

[DOI]

Proceedings of the Algorithms in Bioinformatics, Second International Workshop, 2002

On the Relation between SAT and BDDs for Equivalence Checking.

[BibT_eX]

[DOI]

Rolf Drechsler

Alex Orailoglu

Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

Reducing Test Application Time Through Test Data Mutation Encoding.

[BibT_eX]

[DOI]

Alex Orailoglu

Proceedings of the 2002 Design, 2002

2001

On the use of don't cares during symbolic reachability analysis.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Combinational equivalence checking using Boolean satisfiability and binary decision diagrams.

[BibT_eX]

[DOI]

Ashraf Salem

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000

M-CHECK: a multiple engine combinational equivalence checker.

[BibT_eX]

[DOI]