Shengqi Yu

Orcid: 0000-0001-8059-5793

According to our database1, Shengqi Yu authored at least 9 papers between 2020 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Asymmetric trench SiC MOSFET with integrated channel accumulation diode for enhanced reverse conduction and switching characteristics.
Microelectron. J., 2024

2023
Approximate digital-in analog-out multiplier with asymmetric nonvolatility and low energy consumption.
Integr., November, 2023

IMBUE: In-Memory Boolean-to-CUrrent Inference ArchitecturE for Tsetlin Machines.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

2022
Automated Mapping of Asynchronous Circuits on FPGA under Timing Constraints.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

Editable asynchronous control logic for SAR ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Automated Synthesis of Asynchronous Tsetlin Machines on FPGA.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

2021
Optimized Multi-Memristor Model based Low Energy and Resilient Current-Mode Multiplier Design.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
Self-Amplifying Current-Mode Multiplier Design using a Multi-Memristor Crossbar Cell Structure.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

Current-Mode Carry-Free Multiplier Design using a Memristor-Transistor Crossbar Architecture.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020


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