Shengbing Zhang

Orcid: 0000-0002-2854-729X

According to our database1, Shengbing Zhang authored at least 45 papers between 2004 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
NDPGNN: A Near-Data Processing Architecture for GNN Training and Inference Acceleration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2024

RE-Specter: Examining the Architectural Features of Configurable CNN With Power Side-Channel.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2024

Equalized Aggregation for Heterogeneous Federated Mobile Edge Learning.
IEEE Trans. Mob. Comput., May, 2024

Efficient knowledge management for heterogeneous federated continual learning on resource-constrained edge devices.
Future Gener. Comput. Syst., 2024

Resource-Efficient Heterogenous Federated Continual Learning on Edge.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
A high-efficiency spaceborne processor for hybrid neural networks.
Neurocomputing, July, 2023

Deep Reinforcement Learning-Assisted Optimization for Resource Allocation in Downlink OFDMA Cooperative Systems.
Entropy, March, 2023

A Noise-Driven Heterogeneous Stochastic Computing Multiplier for Heuristic Precision Improvement in Energy-Efficient DNNs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023

Joint heterogeneity-aware personalized federated search for energy efficient battery-powered edge computing.
Future Gener. Comput. Syst., 2023

SaGNN: a Sample-based GNN Training and Inference Hardware Accelerator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022
Memory-Computing Decoupling: A DNN Multitasking Accelerator With Adaptive Data Arrangement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

MemUnison: A Racetrack-ReRAM-Combined Pipeline Architecture for Energy-Efficient in-Memory CNNs.
IEEE Trans. Computers, 2022

A Review of Fundamental Optimization Approaches and the Role of AI Enabling Technologies in Physical Layer Security.
Sensors, 2022

Secure state estimation for event-triggered cyber-physical systems against deception attacks.
J. Frankl. Inst., 2022

DCNN search and accelerator co-design: Improve the adaptability between NAS frameworks and embedded platforms.
Integr., 2022

2021
A Reconfigurable Neural Network Processor With Tile-Grained Multicore Pipeline for Object Detection on FPGA.
IEEE Trans. Very Large Scale Integr. Syst., 2021

A Heterogeneous RISC-V Processor for Efficient DNN Application in Smart Sensing System.
Sensors, 2021

Efficient Resource-Aware Convolutional Neural Architecture Search for Edge Computing with Pareto-Bayesian Optimization.
Sensors, 2021

Position-aware lightweight object detectors with depthwise separable convolutions.
J. Real Time Image Process., 2021

Hardware architecture design of HEVC entropy decoding.
Proceedings of the 2021 IEEE Intl Conf on Parallel & Distributed Processing with Applications, Big Data & Cloud Computing, Sustainable Computing & Communications, Social Computing & Networking (ISPA/BDCloud/SocialCom/SustainCom), New York City, NY, USA, September 30, 2021

A Heterogeneous Stochastic Computing Multiplier for Universally Accurate and Energy-Efficient DNNs.
Proceedings of the 2021 IEEE Intl Conf on Parallel & Distributed Processing with Applications, Big Data & Cloud Computing, Sustainable Computing & Communications, Social Computing & Networking (ISPA/BDCloud/SocialCom/SustainCom), New York City, NY, USA, September 30, 2021

Accuracy vs. Efficiency: Achieving both Through Hardware-Aware Quantization and Reconfigurable Architecture with Mixed Precision.
Proceedings of the 2021 IEEE Intl Conf on Parallel & Distributed Processing with Applications, Big Data & Cloud Computing, Sustainable Computing & Communications, Social Computing & Networking (ISPA/BDCloud/SocialCom/SustainCom), New York City, NY, USA, September 30, 2021

SPACE: Sparsity Propagation Based DCNN Training Accelerator on Edge.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2021

Hardware-Aware NAS Framework with Layer Adaptive Scheduling on Embedded System.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
Dynamic resource adaptation method for airborne network based on multi-objective optimisation.
Int. J. Internet Protoc. Technol., 2020

Research on equilibrium scheduling of airborne network resource based on load Gini coefficient.
Int. J. Inf. Commun. Technol., 2020

Towards Energy Efficient Architecture for Spaceborne Neural Networks Computation.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2020

2019
A Highly Efficient Heterogeneous Processor for SAR Imaging.
Sensors, 2019

Efficient Object Detection Framework and Hardware Architecture for Remote Sensing Images.
Remote. Sens., 2019

2017
A 50 mV Fully-Integrated Self-Startup Circuit for Thermal Energy Harvesting.
J. Circuits Syst. Comput., 2017

2015
A Current Mode Buck/Boost DC-DC Converter With Automatic Mode Transition and Light Load Efficiency Enhancement.
IEICE Trans. Electron., 2015

2014
A High Efficiency Adaptive Current mode Step-up/Step-Down DC-DC Converter with Four Modes for Smooth Transition.
J. Circuits Syst. Comput., 2014

A passive monitoring model for P2P network based on 2D Bloom Filter data verification algorithm.
Proceedings of the 14th International Symposium on Communications and Information Technologies, 2014

Influence of relationship strengths to network structures in social network.
Proceedings of the 14th International Symposium on Communications and Information Technologies, 2014

Analysis and optimization of the system-level simulator.
Proceedings of the IEEE International Conference on Information and Automation, 2014

CUDA-based real-time face recognition system.
Proceedings of the Fourth International Conference on Digital Information and Communication Technology and its Applicationsm DICTAP 2014, 2014

2013
An automatic peak-valley current mode step-up/step-down DC-DC converter with smooth transition.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
DLWAP-buffer: A Novel HW/SW Architecture to Alleviate the Cache Coherence on Streaming-like Data in CMP.
Proceedings of the IEEE 6th International Symposium on Embedded Multicore/Manycore SoCs, 2012

Analog layout retargeting with geometric programming and constrains symbolization method.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Multivariate Process Capability Index with Spatial Coefficient Modification.
Proceedings of the Third International Conference on Digital Manufacturing & Automation, 2012

2008
Dynamically Reconfigurable Instruction Set for Software Radio Encoding/Coding.
Proceedings of the 2008 International Conference on Multimedia and Ubiquitous Engineering (MUE 2008), 2008

2007
Testing of a 32-bit High Performance Embedded Microprocessor.
Proceedings of the IEEE Second International Symposium on Industrial Embedded Systems, 2007

2006
VMSIM: Virtual Machine Based a Full System Simulation Platform for Microprocessors' Functional Verification.
Proceedings of the Third International Conference on Information Technology: New Generations (ITNG 2006), 2006

2005
Microprocessor Based Self Schedule and Parallel BIST for System-On-a-Chip.
Proceedings of the Embedded Software and Systems, Second International Conference, 2005

2004
An Efficient Verification Method for Microprocessors Based on the Virtual Machine.
Proceedings of the Embedded Software and Systems, First International Conference, 2004


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