Shen-Iuan Liu

IEEE Trans. Circuits Syst. II Express Briefs, September, 2024

A 40-Gb/s PAM-3 Receiver With Modified Summer-Merged Slicers and PRTS Checker.

[BibT_eX]

[DOI]

Jhe-En Lin

Yi-Hao Lan

IEEE Trans. Very Large Scale Integr. Syst., August, 2024

A 36-Gb/s 2× Half-Baud-Rate Adaptive Receiver in 28-nm CMOS.

[BibT_eX]

[DOI]

Yi-Hao Lan

IEEE Trans. Very Large Scale Integr. Syst., July, 2024

A 12.93-16 Gb/s Reference-Less Baud-Rate CDR Circuit With One-Tap DFE and Semirotational Frequency Detection.

[BibT_eX]

[DOI]

Hsi-Kai Peng

IEEE Trans. Very Large Scale Integr. Syst., April, 2024

A 0.079-pJ/b/dB 32-Gb/s 2× Half-Baud-Rate CDR Circuit With Frequency Detector.

[BibT_eX]

[DOI]

Yi-Hao Lan

IEEE Trans. Very Large Scale Integr. Syst., April, 2024

A 16-Gb/s Baud-Rate CDR Circuit With One-Tap Speculative DFE and Wide Frequency Capture Range.

[BibT_eX]

[DOI]

Po-Yuan Chou

Wei-Ming Chen

IEEE Trans. Very Large Scale Integr. Syst., March, 2024

2023

A 1.6-GHz DPLL Using Feedforward Phase-Error Cancellation.

[BibT_eX]

[DOI]

Zhi-Heng Kang

IEEE J. Solid State Circuits, March, 2023

2022

A 0.0067-mm2 12-bit 20-MS/s SAR ADC Using Digital Place-and-Route Tools in 40-nm CMOS.

[BibT_eX]

[DOI]

Yao-Hung Tsai

IEEE Trans. Very Large Scale Integr. Syst., 2022

A Wide-Range FD for Referenceless Baud-Rate CDR Circuits.

[BibT_eX]

[DOI]

Chang-Cheng Huang

IEEE Trans. Circuits Syst. II Express Briefs, 2022

A Low-Jitter Sub-Sampling PLL With a Sub-Sampling DLL.

[BibT_eX]

[DOI]

Yuan Cheng Qian

Yen-Yu Chao

IEEE Trans. Circuits Syst. II Express Briefs, 2022

A 1.45-pJ/b 16-Gb/s Edge-Based Sub-Baud-Rate Digital CDR Circuit.

[BibT_eX]

[DOI]

Wen-Chi Huang

IEEE Trans. Circuits Syst. II Express Briefs, 2022

A 20-Gb/s Jitter-Tolerance-Enhanced Digital CDR With One-Tap DFE.

[BibT_eX]

[DOI]

Wei-Ming Chen

IEEE Trans. Circuits Syst. II Express Briefs, 2022

A 2-3 GHz Fast-Locking PLL Using Phase Error Compensator.

[BibT_eX]

[DOI]

Jia-Rong Chang

IEEE Trans. Circuits Syst. II Express Briefs, 2022

An Injection-Locked Clock Multiplier With Injection Strength Calibration.

[BibT_eX]

[DOI]

Yen-Min Tseng

Yu-Chi Yen

Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022

An Adaptive Digital PLL Based on BBPFD Transition Probability.

[BibT_eX]

[DOI]

Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022

2021

A Jitter-Tolerance-Enhanced Digital CDR Circuit Using Background Loop Gain Controller.

[BibT_eX]

[DOI]

Chang-Cheng Huang

IEEE Trans. Circuits Syst. II Express Briefs, 2021

A 2.4-3.0GHz Process-Tolerant Sub-Sampling PLL With Loop Bandwidth Calibration.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

A Type-I PLL With Foreground Loop Bandwidth Calibration.

[BibT_eX]

[DOI]

Ming-Han Chou

IEEE Trans. Circuits Syst. II Express Briefs, 2021

A 5-Gb/s Adaptive Digital CDR Circuit With SSC Capability and Enhanced High-Frequency Jitter Tolerance.

[BibT_eX]

[DOI]

Shun-Chi Chang

IEEE Trans. Circuits Syst. II Express Briefs, 2021

A 10.4-16-Gb/s Reference-Less Baud-Rate Digital CDR With One-Tap DFE Using a Wide-Range FD.

[BibT_eX]

[DOI]

Wei-Ming Chen

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A Digital Phase-Locked Loop With Background Supply Noise Cancellation.

[BibT_eX]

[DOI]

Yen-Min Tseng

Yu-Chi Yen

Proceedings of the International Symposium on VLSI Design, Automation and Test, 2021

An Adaptive Loop Gain Tracking Digital PLL Using Spectrum-Balancing Technique.

[BibT_eX]

[DOI]

Guan-Yu Su

Zhi-Heng Kang

Proceedings of the International Symposium on VLSI Design, Automation and Test, 2021

2020

A 64-Gb/s PAM-4 Optical Receiver With Amplitude/Phase Correction and Threshold Voltage/Data Level Calibration.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

A 2.4-GHz Area-Efficient and Fast-Locking Subharmonically Injection-Locked Type-I PLL.

[BibT_eX]

[DOI]

Ming-Han Chou

IEEE Trans. Very Large Scale Integr. Syst., 2020

A 1.22 mW 2.4 GHz PLL Using a Single-Ring-Oscillator-Based Integrator With Background Frequency Calibration.

[BibT_eX]

[DOI]

Guan-Yu Su

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

A 13.56 MHz Current-Mode Wireless Power Receiver With Energy-Investment Capability.

[BibT_eX]

[DOI]

Chung-Jen Kuo

IEEE Trans. Circuits Syst. II Express Briefs, 2020

An Indoor Photovoltaic Energy Harvester Using Time-Based MPPT and On-Chip Photovoltaic Cell.

[BibT_eX]

[DOI]

Ming-Chia Chang

IEEE Trans. Circuits Syst., 2020

A 500nW-50μ W Indoor Photovoltaic Energy Harvester with Multi-mode MPPT.

[BibT_eX]

[DOI]

Ming-Chia Chang

Min-Hsuan Wu

Proceedings of the 2020 International Symposium on VLSI Design, Automation and Test, 2020

2019

A 2.4-GHz Frequency-Drift-Compensated Phase-Locked Loop With 2.43 ppm/°C Temperature Coefficient.

[BibT_eX]

[DOI]

Cheng-En Hsieh

IEEE Trans. Very Large Scale Integr. Syst., 2019

A PVT-Tolerant MDLL Using a Frequency Calibrator and a Voltage Monitor.

[BibT_eX]

[DOI]

Yu-Kai Chiu

IEEE Trans. Very Large Scale Integr. Syst., 2019

A 13.4-MHz Relaxation Oscillator With Temperature Compensation.

[BibT_eX]

[DOI]

Yi-An Chang

IEEE Trans. Very Large Scale Integr. Syst., 2019

An On-Chip Relaxation Oscillator With Comparator Delay Compensation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

A PVT-Tolerant Injection-Locked Clock Multiplier With a Frequency Calibrator Using a Delay Time Detector.

[BibT_eX]

[DOI]

Che-Wei Tien

IEEE Trans. Circuits Syst. II Express Briefs, 2019

A Sub-Sampling PLL with Robust Operation under Supply Interference and Short Re-Locking Time.

[BibT_eX]

[DOI]

Yuan Cheng Qian

Yen-Yu Chao

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018

A Digital Phase-Locked Loop With Background Supply Voltage Sensitivity Minimization.

[BibT_eX]

[DOI]

Che-Wei Tien

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Development of 400 Gb/s optical transceivers for SMF based datacenter optical interconnect.

[BibT_eX]

[DOI]

Proceedings of the 27th Wireless and Optical Communication Conference, 2018

A 13.56 MHz 88.7%-PCE Voltage Doubling Rectifier Using Adaptive Delay Time and Pulse-Width Control.

[BibT_eX]

[DOI]

Ye-Sing Luo

Hsing-Hung Lin

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017

A 2.25-2.7 GHz Area-Efficient Subharmonically Injection-Locked Fractional-N Frequency Synthesizer With a Fast-Converging Correlation Loop.

[BibT_eX]

[DOI]

Yen-Hsiang Tseng

Che-Wei Yeh

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

A 5 Gb/s Voltage-Mode Transmitter Using Adaptive Time-Based De-Emphasis.

[BibT_eX]

[DOI]

Wun-Jian Su

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

A 0.31-pJ/bit 20-Gb/s DFE With 1 Discrete Tap and 2 IIR Filters Feedback in 40-nm-LP CMOS.

[BibT_eX]

[DOI]

Kuan-Yu Chen

Wei-Yung Chen

IEEE Trans. Circuits Syst. II Express Briefs, 2017

A 0.035-pJ/bit/dB 20-Gb/s Adaptive Linear Equalizer With an Adaptation Time of 2.68 µs.

[BibT_eX]

[DOI]

Kuan-Yu Chen

Wei-Yung Chen

IEEE Trans. Circuits Syst. II Express Briefs, 2017

A Voltage Multiplier With Adaptive Threshold Voltage Compensation.

[BibT_eX]

[DOI]

Ye-Sing Luo

IEEE J. Solid State Circuits, 2017

A 56Gbps PAM-4 optical receiver front-end.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016

A 12-bit 3.4 MS/s Two-Step Cyclic Time-Domain ADC in 0.18-µm CMOS.

[BibT_eX]

[DOI]

Liang-Jen Chen

IEEE Trans. Very Large Scale Integr. Syst., 2016

A Digital PLL Using Oversampling Delta-Sigma TDC.

[BibT_eX]

[DOI]

Chih-Lu Wei

IEEE Trans. Circuits Syst. II Express Briefs, 2016

A 10-bit 40-MS/s Time-Domain Two-Step ADC With Short Calibration Time.

[BibT_eX]

[DOI]

Liang-Jen Chen

IEEE Trans. Circuits Syst. II Express Briefs, 2016

A Bang Bang Phase-Locked Loop Using Automatic Loop Gain Control and Loop Latency Reduction Techniques.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2016

A 6.7 MHz to 1.24 GHz 0.0318 mm 2 Fast-Locking All-Digital DLL Using Phase-Tracing Delay Unit in 90 nm CMOS.

[BibT_eX]

[DOI]

Min-Han Hsieh

Liang-Hsin Chen

Charlie Chung-Ping Chen

IEEE J. Solid State Circuits, 2016

19.5 A 3.2GHz digital phase-locked loop with background supply-noise cancellation.

[BibT_eX]

[DOI]

Che-Wei Yeh

Cheng-En Hsieh

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

A digital MDLL using switched biasing technique to reduce low-frequency phase noise.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015

A Subharmonically Injection-Locked All-Digital PLL Without Main Divider.

[BibT_eX]

[DOI]

Kai-Hui Zeng

IEEE Trans. Circuits Syst. II Express Briefs, 2015

A Subharmonically Injection-Locked PLL With Calibrated Injection Pulsewidth.

[BibT_eX]

[DOI]

Chih-Lu Wei

IEEE Trans. Circuits Syst. II Express Briefs, 2015

A Loop Gain Optimization Technique for Integer-N TDC-Based Phase-Locked Loops.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A digital bang-bang phase-locked loop with automatic loop gain control and loop latency reduction.

[BibT_eX]

[DOI]

Proceedings of the Symposium on VLSI Circuits, 2015

A digital bang-bang phase-locked loop with bandwidth calibration.

[BibT_eX]

[DOI]

Chi-Huan Chiang

Chang-Cheng Huang

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014

An All-Digital Despreading Clock Generator.

[BibT_eX]

[DOI]

Shih-Han Ku

IEEE Trans. Circuits Syst. II Express Briefs, 2014

A 3-25 Gb/s Four-Channel Receiver With Noise-Canceling TIA and Power-Scalable LA.

[BibT_eX]

[DOI]

Yu-Hsun Chien

IEEE Trans. Circuits Syst. II Express Briefs, 2014

Nanopower CMOS Relaxation Oscillators With Sub-100 ppm°C Temperature Coefficient.

[BibT_eX]

[DOI]

Yu-Hsuan Chiang

IEEE Trans. Circuits Syst. II Express Briefs, 2014

A silicon nanowire-based bio-sensing system with digitized outputs for acute myocardial infraction diagnosis.

[BibT_eX]

[DOI]

Proceedings of IEEE-EMBS International Conference on Biomedical and Health Informatics, 2014

A low-input-swing AC-DC voltage multiplier using Schottky diodes.

[BibT_eX]

[DOI]

Ye-Sing Luo

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

A 5-20 Gb/s power scalable adaptive linear equalizer using edge counting.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

A 0.43pJ/bit true random number generator.

[BibT_eX]

[DOI]

Yu-Hsuan Chiang

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

A 2×25 Gb/s clock and data recovery with background amplitude-locked loop.

[BibT_eX]

[DOI]

Chien-Kai Kao

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

A 0.3V 10bit 7.3fJ/conversion-step SAR ADC in 0.18μm CMOS.

[BibT_eX]

[DOI]

Cheng-En Hsieh

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013

A Wide-Range PLL Using Self-Healing Prescaler/VCO in 65-nm CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Ultrasonic Power/Data Telemetry and Neural Stimulator With OOK-PM Signaling.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2013

4-Gb/s Parallel Receivers With Adaptive FEXT Cancellation by Pulse Width and Amplitude Calibrations.

[BibT_eX]

[DOI]

Yan-Yu Lin

IEEE Trans. Circuits Syst. II Express Briefs, 2013

4-Gb/s Parallel Receivers With Adaptive Far-End Crosstalk Cancellation.

[BibT_eX]

[DOI]

Yan-Yu Lin

IEEE Trans. Circuits Syst. II Express Briefs, 2013

A 4.8-GHz Dividerless Subharmonically Injection-Locked All-Digital PLL With a FOM of -252.5 dB.

[BibT_eX]

[DOI]

Kai-Hui Zeng

IEEE Trans. Circuits Syst. II Express Briefs, 2013

An All-Digital Spread-Spectrum Clock Generator With Self-Calibrated Bandwidth.

[BibT_eX]

[DOI]

Shih-Han Ku

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A Submicrowatt 1.1-MHz CMOS Relaxation Oscillator With Temperature Compensation.

[BibT_eX]

[DOI]

Yu-Hsuan Chiang

IEEE Trans. Circuits Syst. II Express Briefs, 2013

A 10-Gb/s Adaptive Parallel Receiver With Joint XTC and DFE Using Power Detection.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2013

A 7.5-Gb/s One-Tap-FFE Transmitter With Adaptive Far-End Crosstalk Cancellation Using Duty Cycle Detection.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2013

A 2.4-GHz Subharmonically Injection-Locked PLL With Self-Calibrated Injection Timing.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2013

Divide-by-Three Injection-Locked Frequency Dividers Over 200 GHz in 40-nm CMOS.

[BibT_eX]

[DOI]

Pin-Hao Feng

IEEE J. Solid State Circuits, 2013

Ultrasonic telemetry and neural stimulator with FSK-PWM signaling.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012

A 104-GHz Phase-Locked Loop Using a VCO at Second Pole Frequency.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

A 6-GHz All-Digital Fractional-N Frequency Synthesizer Using FIR-Embedded Noise Filtering Technique.

[BibT_eX]

[DOI]

Hung-Yu Lu

IEEE Trans. Circuits Syst. II Express Briefs, 2012

G-Band Injection-Locked Frequency Dividers Using π-type LC Networks.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

An All-Digital Jitter Tolerance Measurement Technique for CDR Circuits.

[BibT_eX]

[DOI]

Ping-Ying Wang

IEEE Trans. Circuits Syst. II Express Briefs, 2012

Inductorless Wideband CMOS Low-Noise Amplifiers Using Noise-Canceling Technique.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Introduction to the Special Section on the 2011 Asian Solid-State Circuits Conference (A-SSCC).

[BibT_eX]

[DOI]

Tsung-Hsien Lin

Woogeun Rhee

IEEE J. Solid State Circuits, 2012

A Leakage-Current-Recycling Phase-Locked Loop in 65 nm CMOS Technology.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2012

A fast-locking phase-locked loop using CP control and gated VCO.

[BibT_eX]

[DOI]

Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

A 2.4GHz sub-harmonically injection-locked PLL with self-calibrated injection timing.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 6.7MHz-to-1.24GHz 0.0318mm2 fast-locking all-digital DLL in 90nm CMOS.

[BibT_eX]

[DOI]

Min-Han Hsieh

Liang-Hsin Chen

Charlie Chung-Ping Chen

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011

A Digitally-Calibrated Phase-Locked Loop With Supply Sensitivity Suppression.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

A 132.6-GHz Phase-Locked Loop in 65 nm Digital CMOS.

[BibT_eX]

[DOI]

Bo-Yu Lin

IEEE Trans. Circuits Syst. II Express Briefs, 2011

A 40-GHz Fast-Locked All-Digital Phase-Locked Loop Using a Modified Bang-Bang Algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2011

A Noise Filtering Technique for Fractional-N Frequency Synthesizers.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2011

A Rail-to-Rail Class-B Buffer With DC Level-Shifting Current Mirror and Distributed Miller Compensation for LCD Column Drivers.

[BibT_eX]

[DOI]

Wei-Jen Huang

Shigeisa Nagayasu

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Decision Feedback Equalizers Using the Back-Gate Feedback Technique.

[BibT_eX]

[DOI]

Chang-Lin Hsieh

IEEE Trans. Circuits Syst. II Express Briefs, 2011

A 1-16-Gb/s Wide-Range Clock/Data Recovery Circuit With a Bidirectional Frequency Detector.

[BibT_eX]

[DOI]

Chang-Lin Hsieh

IEEE Trans. Circuits Syst. II Express Briefs, 2011

Analysis and Design of D-Band Injection-Locked Frequency Dividers.

[BibT_eX]

[DOI]

Bo-Yu Lin

IEEE J. Solid State Circuits, 2011

A 20Gb/s digitally adaptive equalizer/DFE with blind sampling.

[BibT_eX]

[DOI]

Yu-Ming Ying

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 6Gb/s receiver with 32.7dB adaptive DFE-IIR equalization.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

3.6mW D-band divide-by-3 injection-locked frequency dividers in 65nm CMOS.

[BibT_eX]

[DOI]

Chiao-Hsing Wang

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

A leakage-current-recycling phase-locked loop in 65nm CMOS technology.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010

A 20-Gb/s Transmitter With Adaptive Preemphasis in 65-nm CMOS Technology.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2010

A 1.62/2.7-Gb/s Adaptive Transmitter With Two-Tap Preemphasis Using a Propagation-Time Detector.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2010

A 10-MS/s-to-100-kS/s Power-Scalable Fully Differential CBSC 10-Bit Pipelined ADC With Adaptive Biasing.

[BibT_eX]

[DOI]

Mu-Chen Huang

IEEE Trans. Circuits Syst. II Express Briefs, 2010

A Phase-Locked Loop With Background Leakage Current Compensation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2010

A Merged CMOS Digital Near-End Crosstalk Canceller and Analog Equalizer for Multi-Lane Serial-Link Receivers.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2010

2009

An 8-bit 20-MS/s ZCBC Time-Domain Analog-to-Digital Data Converter.

[BibT_eX]

[DOI]

I-Hsin Wang

IEEE Trans. Circuits Syst. II Express Briefs, 2009

A 50-Gb/s 10-mW Analog Equalizer Using Transformer Feedback Technique in 65-nm CMOS Technology.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2009

Comments on "A 10-Gb/s Inductorless CMOS Analog Equalizer With an Interleaved Active Feedback Topology".

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2009

A 10-Gb/s Inductorless CMOS Analog Equalizer With an Interleaved Active Feedback Topology.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2009

A Phase-Locked Loop With Self-Calibrated Charge Pumps in 3- muhboxm LTPS-TFT Technology.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2009

A 104- to 112.8-GHz CMOS Injection-Locked Frequency Divider.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2009

A Leakage-Compensated PLL in 65-nm CMOS Technology.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2009

A Fully Differential Comparator-Based Switched-Capacitor DeltaSigma Modulator.

[BibT_eX]

[DOI]

Mu-Chen Huang

IEEE Trans. Circuits Syst. II Express Briefs, 2009

A 20-MHz to 3-GHz Wide-Range Multiphase Delay-Locked Loop.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2009

A Single-PLL UWB Frequency Synthesizer Using Multiphase Coupled Ring Oscillator and Current-Reused Multiplier.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2009

A 1.5 GHz All-Digital Spread-Spectrum Clock Generator.

[BibT_eX]

[DOI]

Sheng-You Lin

IEEE J. Solid State Circuits, 2009

A 33.6-to-33.8 Gb/s Burst-Mode CDR in 90 nm CMOS Technology.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2009

A 1.5 GHz phase-locked loop with leakage current suppression in 65 nm CMOS.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2009

A 43.7mW 96GHz PLL in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A 128.24-to-137.00GHz injection-locked frequency divider in 65nm CMOS.

[BibT_eX]

[DOI]

Bo-Yu Lin

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A leakage-suppression technique for phase-locked systems in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A 140MS/s 10-bit Pipelined ADC with a Folded S/H Stage.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008

A 0.18-muhbox m CMOS 1.25-Gbps Automatic-Gain-Control Amplifier.

[BibT_eX]

[DOI]

I-Hsin Wang

IEEE Trans. Circuits Syst. II Express Briefs, 2008

Full-Rate Bang-Bang Phase/Frequency Detectors for Unilateral Continuous-Rate CDRs.

[BibT_eX]

[DOI]

Shao-Hung Lin

IEEE Trans. Circuits Syst. II Express Briefs, 2008

An All-Digital Fast-Locking Programmable DLL-Based Clock Generator.

[BibT_eX]

[DOI]

Chuan-Kang Liang

IEEE Trans. Circuits Syst. I Regul. Pap., 2008

10-Gb/s Inductorless CDRs With Digital Frequency Calibration.

[BibT_eX]

[DOI]

Hong-Lin Chu

IEEE Trans. Circuits Syst. I Regul. Pap., 2008

A 50.8-53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13- mum CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2008

A Delay-Locked Loop With Statistical Background Calibration.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2008

A 3-8 GHz Delay-Locked Loop With Cycle Jitter Calibration.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2008

Introduction to the Special Issue on the 2008 IEEE International Solid-State Circuits Conference.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2008

A 40 Gb/s CMOS Serial-Link Receiver With Adaptive Equalization and Clock/Data Recovery.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2008

40 Gb/s Transimpedance-AGC Amplifier and CDR Circuit for Broadband Data Receivers in 90 nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2008

A Jitter-Tolerance-Enhanced CDR Using a GDCO-Based Phase Detector.

[BibT_eX]

[DOI]

Sy-Chyuan Hwu

IEEE J. Solid State Circuits, 2008

A Digital Calibration Technique for Charge Pumps in Phase-Locked Systems.

[BibT_eX]

[DOI]

Shin-Hua Chen

IEEE J. Solid State Circuits, 2008

An Infinite Phase Shift Delay-Locked Loop With Voltage-Controlled Sawtooth Delay Line.

[BibT_eX]

[DOI]

Chao-Chyun Chen

IEEE J. Solid State Circuits, 2008

Capacitor-free low dropout regulators using nested Miller compensation with active resistor and 1-bit programmable capacitor array.

[BibT_eX]

[DOI]

Wei-Jen Huang

IET Circuits Devices Syst., 2008

3.5mW W-Band Frequency Divider with Wide Locking Range in 90nm CMOS Technology.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A 40Gb/s CMOS Serial-Link Receiver with Adaptive Equalization and CDR.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A 20/10/5/2.5Gb/s Power-scaling Burst-Mode CDR Circuit Using GVCO/Div2/DFF Tri-mode Cells.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007

A Low-Jitter Spread Spectrum Clock Generator Using FDMP.

[BibT_eX]

[DOI]

Ding-Shiuan Shen

IEEE Trans. Circuits Syst. II Express Briefs, 2007

Spur-Suppression Techniques for Frequency Synthesizers.

[BibT_eX]

[DOI]

Hsin-Hua Chen

IEEE Trans. Circuits Syst. II Express Briefs, 2007

A 62.5-625-MHz Anti-Reset All-Digital Delay-Locked Loop.

[BibT_eX]

[DOI]

Bo-Jiun Chen

IEEE Trans. Circuits Syst. II Express Briefs, 2007

A Time-Constant Calibrated Phase-Locked Loop With a Fast-Locked Time.

[BibT_eX]

[DOI]

Sung-Rung Han

IEEE Trans. Circuits Syst. II Express Briefs, 2007

A 0.5-5-GHz Wide-Range Multiphase DLL With a Calibrated Charge Pump.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2007

An Ultra-Wide-Band 0.4-10-GHz LNA in 0.18-μm CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2007

A DLL-Based Variable-Phase Clock Buffer.

[BibT_eX]

[DOI]

Chao-Chyun Chen

IEEE Trans. Circuits Syst. II Express Briefs, 2007

A 2.5 GHz All-Digital Delay-Locked Loop in 0.13 µm CMOS Technology.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2007

A 40-550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2007

A Broadband Noise-Canceling CMOS LNA for 3.1-10.6-GHz UWB Receivers.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2007

A 1.2-V 37-38.5-GHz Eight-Phase Clock Generator in 0.13-µm CMOS Technology.

[BibT_eX]

[DOI]

Lan-Chou Cho

IEEE J. Solid State Circuits, 2007

A Multi-Band Burst-Mode Clock and Data Recovery Circuit.

[BibT_eX]

[DOI]

Sy-Chyuan Hwu

IEICE Trans. Electron., 2007

A 7-BIT 400MS/s sub-ranging flash ADC in 0.18um CMOS.

[BibT_eX]

[DOI]

I-Hsin Wang

Proceedings of the 2007 IEEE International SOC Conference, 2007

A 10-BIT 100MS/s pipelined ADC IN 0.18μm CMOS technology.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International SOC Conference, 2007

A 40Gb/s Transimpedance-AGC Amplifier with 19dB DR in 90nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A 58-to-60.4GHz Frequency Synthesizer in 90nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A 40GHz DLL-Based Clock Generator in 90nm CMOS Technology.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A 33.6-to-33.8Gb/s Burst-Mode CDR in 90nm CMOS.

[BibT_eX]

[DOI]

Lan-Chou Cho

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A 2.4GHz Efficiency-Enhanced Rectifier for Wireless Telemetry.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

A 200-Mbps∼2-Gbps continuous-rate clock-and-data-recovery circuit.

[BibT_eX]

[DOI]

Kuan-Hua Chao

IEEE Trans. Circuits Syst. I Regul. Pap., 2006

A spur-reduction technique for a 5-GHz frequency synthesizer.

[BibT_eX]

[DOI]

Chun-Yi Kuo

IEEE Trans. Circuits Syst. I Regul. Pap., 2006

All-Digital Fast-Locked Synchronous Duty-Cycle Corrector.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2006

A 155.52 mbps-3.125 gbps continuous-rate clock and data recovery circuit.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2006

All-digital delay-locked loop/pulsewidth-control loop with adjustable duty cycles.

[BibT_eX]

[DOI]

You-Jen Wang

IEEE J. Solid State Circuits, 2006

A Calibrated Pulse Generator for Impulse-Radio UWB Applications.

[BibT_eX]

[DOI]

Shih-Tsai Liu

IEEE J. Solid State Circuits, 2006

A 0.7-2-GHz self-calibrated multiphase delay-locked loop.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2006

All-Digital Clock Deskew Buffer with Variable Duty Cycles.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2006

A 1 V Phase Locked Loop with Leakage Compensation in 0.13 µm CMOS Technology.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2006

A 10Gb/s CMOS AGC Amplifier with 35dB Dynamic Range for 10Gb Ethernet.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A 14-band Frequency Synthesizer for MB-OFDM UWB Application.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A 10Gbps Burst-Mode CDR Circuit in 0.18μm CMOS.

[BibT_eX]

[DOI]

Sy-Chyuan Hwu

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

A 44GHz Dual-Modulus Divide-by-4/5 Prescaler in 90nm CMOS Technology.

[BibT_eX]

[DOI]

Lan-chou Cho

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005

Selective metal parallel shunting inductor and its VCO application.

[BibT_eX]

[DOI]

Chun-Yi Kuo

IEEE Trans. Circuits Syst. I Regul. Pap., 2005

CMOS current-mode divider and its applications.

[BibT_eX]

[DOI]

Weihsing Liu

Shui-Ken Wei

IEEE Trans. Circuits Syst. II Express Briefs, 2005

CMOS wideband amplifiers using multiple inductive-series peaking technique.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2005

A single-path pulsewidth control loop with a built-in delay-locked loop.

[BibT_eX]

[DOI]

Sung-Rung Han

IEEE J. Solid State Circuits, 2005

A wide-range and fast-locking all-digital cycle-controlled delay-locked loop.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2005

A Fully Integrated 1.7-3.125 Gbps Clock and Data Recovery Circuit Using a Gated Frequency Detector.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2005

A Wide-Range Multiphase Delay-Locked Loop Using Mixed-Mode VCDLs.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2005

A 15 mW 69 dB 2 Gsamples/s CMOS analog front-end for low-band UWB applications.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A tunable bandpass ΔΣ modulator using double sampling.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A broadband noise-canceling CMOS LNA for 3.1-10.6-GHz UWB receiver.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004

Low jitter and multirate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2004

A 3.125-Gb/s clock and data recovery circuit for the 10-Gbase-LX4 Ethernet.

[BibT_eX]

[DOI]

Shang-Ping Chen

IEEE J. Solid State Circuits, 2004

A low voltage-power 13-bit 16 MSPS CMOS pipelined ADC.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2004

A 1-V 10.7-MHz fourth-order bandpass ΔΣ modulators using two switched op amps.

[BibT_eX]

[DOI]

Chien-Hung Kuo

IEEE J. Solid State Circuits, 2004

A 500-MHz-1.25-GHz fast-locking pulsewidth control loop with presettable duty cycle.

[BibT_eX]

[DOI]

Sung-Rung Han

IEEE J. Solid State Circuits, 2004

A 1V 4.2mW fully integrated 2.5Gb/s CMOS limiting amplifier using folded active inductors.

[BibT_eX]

[DOI]

Jieh-Wei Liao

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003

Analysis of on-chip spiral inductors using the distributed capacitance model.

[BibT_eX]

[DOI]

Chih-Chun Tang

IEEE J. Solid State Circuits, 2003

A fast locking and low jitter delay-locked loop using DHDL.

[BibT_eX]

[DOI]

Jyh-Woei Lin

IEEE J. Solid State Circuits, 2003

A spread-spectrum clock generator with triangular modulation.

[BibT_eX]

[DOI]

I-Hui Hua

IEEE J. Solid State Circuits, 2003

CMOS Tunable 1/x Circuit and Its Applications.

[BibT_eX]

[DOI]

Weihsing Liu

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

A shifted-averaging VCO with precise multiphase outputs and low jitter operation.

[BibT_eX]

[DOI]

Shang-Ping Chen

Proceedings of the ESSCIRC 2003, 2003

2002

Miniature 3-D inductors in standard CMOS process.

[BibT_eX]

[DOI]

Chih-Chun Tang

IEEE J. Solid State Circuits, 2002

A wide-range delay-locked loop with a fixed latency of one clock cycle.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2002

CMOS 2.4-GHz receiver front end with area-efficient inductors and digitally calibrated 90° delay network.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delay.

[BibT_eX]

[DOI]

Jyh-Woei Lin

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2001

A one-wire approach for skew-compensating clock distribution based on bidirectional techniques.

[BibT_eX]

[DOI]

Ching-Yuan Yang

IEEE J. Solid State Circuits, 2001

An 8-bit 10 MS/s folding and interpolating ADC using the continuous-time auto-zero technique.

[BibT_eX]

[DOI]

Ming-Huang Liu

IEEE J. Solid State Circuits, 2001

CMOS oversampling ΔΣ magnetic-to-digital converters.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2001

A fast-lock mixed-mode DLL using a 2-b SAR algorithm.

[BibT_eX]

[DOI]

Guang-Kaai Dehng

Jyh-Woei Lin

IEEE J. Solid State Circuits, 2001

A CMOS 400-Mb/s serial link for AS-memory systems using a PWM scheme.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2001

CMOS oversampling Sigma-Delta magnetic to digital converters.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000

Fast-switching frequency synthesizer with a discriminator-aided phase detector.

[BibT_eX]

[DOI]

Ching-Yuan Yang

IEEE J. Solid State Circuits, 2000

A double-sampling pseudo-two-path bandpass ΔΣ modulator.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2000

A 900-MHz 1-V CMOS frequency synthesizer.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2000

Clock-deskew buffer using a SAR-controlled delay-locked loop.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2000

1999

Low-power clock-deskew buffer for high-speed digital circuits.

[BibT_eX]

[DOI]

Jiunn-Hwa Lee

Hen-Wai Tsao

IEEE J. Solid State Circuits, 1999

A cyclic CMOS time-to-digital converter with deep sub-nanosecond resolution.

[BibT_eX]

[DOI]

Poki Chen

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1998

New dynamic flip-flops for high-speed dual-modulus prescaler.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 1998

1994

CMOS four-quadrant multiplier using bias feedback techniques.

[BibT_eX]

[DOI]