Sheikh Ariful Islam

Orcid: 0000-0002-3127-3760

According to our database1, Sheikh Ariful Islam authored at least 26 papers between 2018 and 2022.

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Bibliography

2022
Reliability and Security of Extreme Parallelism.
IEEE Consumer Electron. Mag., 2022

Multi-Operator Intelligent UAV Delivery Networks in Beyond Visual Line of Sight Operations.
Proceedings of the 19th IEEE Annual Consumer Communications & Networking Conference, 2022

Introduction and Background.
Behavioral Synthesis for Hardware Security, 2022

Hardware Trojan Localization: Modeling and Empirical Approach.
Behavioral Synthesis for Hardware Security, 2022

Behavioral Synthesis of Key-Obfuscated RTL IP.
Behavioral Synthesis for Hardware Security, 2022

2021
High-Level Synthesis of Key-Obfuscated RTL IP with Design Lockout and Camouflaging.
ACM Trans. Design Autom. Electr. Syst., 2021

Security and Reliability of Safety-Critical RTOS.
SN Comput. Sci., 2021

Partial evaluation based triple modular redundancy for single event upset mitigation.
Integr., 2021

Differentially Private Data Publication with Multi-level Data Utility.
CoRR, 2021

Defending Against Misspeculation-based Cache Probe Attacks Using Variable Record Table.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Analysis of Network Protocols for Secure Communication.
Proceedings of the 9th International Symposium on Digital Forensics and Security, 2021

2020
Interval Arithmetic and Self-Similarity Based RTL Input Vector Control for Datapath Leakage Minimization.
ACM Trans. Design Autom. Electr. Syst., 2020

Gate Level NBTI and Leakage Co-Optimization in Combinational Circuits with Input Vector Cycling.
IEEE Trans. Emerg. Top. Comput., 2020

A Framework for Hardware Trojan Vulnerability Estimation and Localization in RTL Designs.
J. Hardw. Syst. Secur., 2020

Basic Block Encoding Based Run-time CFI Check for Embedded Software.
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

SafeController: Efficient and Transparent Control-Flow Integrity for RTL Design.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Analytical Estimation and Localization of Hardware Trojan Vulnerability in RTL Designs.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

2019
Socio-network Analysis of RTL Designs for Hardware Trojan Localization.
CoRR, 2019

On the (In)security of Approximate Computing Synthesis.
CoRR, 2019

Variable Record Table: A Run-time Solution for Mitigating Buffer Overflow Attack.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

An SR Flip-Flop based Physical Unclonable Functions for Hardware Security.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

Machine Learning Based IoT Edge Node Security Attack and Countermeasures.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

DLockout: A Design Lockout Technique for Key Obfuscated RTL IP Designs.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019

2018
High-level synthesis of key based obfuscated RTL datapaths.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

An Efficient Hardware-Oriented Runtime Approach for Stack-based Software Buffer Overflow Attacks.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2018

Empirical Word-Level Analysis of Arithmetic Module Architectures for Hardware Trojan Susceptibility.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2018


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