Shayan Shahramian

According to our database, Shayan Shahramian authored at least 11 papers between 2011 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

Drawing Inductor Layout with a Reinforcement Learning Agent: Method and Application for VCO Inductors.

Cameron Haigh, Zichen Zhang, Negar Hassanpour, Khurram Javed, Yingying Fu, Shayan Shahramian, Shawn Zhang, Jun Luo

CoRR, 2022

2021

Pre-FEC and Post-FEC BER as Criteria for Optimizing Wireline Transceivers.

Ming Yang, Shayan Shahramian, Henry Wong, Peter Krotnev, Anthony Chan Carusone

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020

Statistical BER Analysis of Wireline Links With Non-Binary Linear Block Codes Subject to DFE Error Propagation.

Ming Yang, Shayan Shahramian, Hossein Shakiba, Henry Wong, Peter Krotnev, Anthony Chan Carusone

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

2019

A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS.

Shayan Shahramian, Behzad Dehlaghi, Joshua Liang, Ryan Bespalko, Dustin Dunwell, James Bailey, Bo Wang, Alireza Sharif Bakhtiar, Michael O'Farrell, Kerry Tang, Anthony Chan Carusone, David Cassan, Davide Tonietto

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2016

Edge-Based Adaptation for a 1 IIR + 1 Discrete-Time Tap DFE Converging in 5~µs.

Shayan Shahramian, Behzad Dehlaghi, Anthony Chan Carusone

IEEE J. Solid State Circuits, 2016

23.7 A 16Gb/s 1 IIR + 1 DT DFE compensating 28dB loss with edge-based adaptation converging in 5µs.

Shayan Shahramian, Behzad Dehlaghi, Anthony Chan Carusone

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015

Correction to "A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS".

Shayan Shahramian, Anthony Chan Carusone

IEEE J. Solid State Circuits, 2015

A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS.

Shayan Shahramian, Anthony Chan Carusone

IEEE J. Solid State Circuits, 2015

2014

A 10Gb/s 4.1mW 2-IIR + 1-discrete-tap DFE in 28nm-LP CMOS.

Shayan Shahramian, Anthony Chan Carusone

Proceedings of the ESSCIRC 2014, 2014

2012

Decision Feedback Equalizer Architectures With Multiple Continuous-Time Infinite Impulse Response Filters.

Shayan Shahramian, Hemesh Yasotharan, Anthony Chan Carusone

IEEE Trans. Circuits Syst. II Express Briefs, 2012

2011

A pattern-guided adaptive equalizer in 65nm CMOS.

Shayan Shahramian, Clifford Ting, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune

Proceedings of the IEEE International Solid-State Circuits Conference, 2011