Shashikanth Bobba
According to our database1,
Shashikanth Bobba
authored at least 17 papers
between 2005 and 2015.
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Bibliography
2015
Layout Technique for Double-Gate Silicon Nanowire FETs With an Efficient Sea-of-Tiles Architecture.
IEEE Trans. Very Large Scale Integr. Syst., 2015
2014
System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits.
ACM J. Emerg. Technol. Comput. Syst., 2014
2013
Cell transformations and physical design techniques for 3D monolithic integrated circuits.
ACM J. Emerg. Technol. Comput. Syst., 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs.
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012
Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistors.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012
Physical synthesis onto a Sea-of-Tiles with double-gate silicon nanowire transistors.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
2011
CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
Design of a CNFET array for sensing and control in P450 based biochips for multiple drug detection.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 17th IEEE International Conference on Electronics, 2010
Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement.
Proceedings of the 47th Design Automation Conference, 2010
Proceedings of the IEEE International Conference on 3D System Integration, 2010
2009
Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis.
Proceedings of the Design, Automation and Test in Europe, 2009
2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
2005
Design of a novel type of on-chip transformer suitable for baluns in customary BICMOS/CMOS technologies.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005