Shashi Kumar

Proceedings of the 2018 4th International Conference on Recent Advances in Information Technology (RAIT), 2018

Remote Compositional Pyroxene Estimates in the Reiner Gamma Formation Using Feature-Oriented Pca: New Insights Into Lunar Swirls.

[BibT_eX]

[DOI]

Shashwat Shukla

Proceedings of the 2018 IEEE International Geoscience and Remote Sensing Symposium, 2018

Sensitivity Enhancement of Current Mirror Readout Circuit Based Piezoresistive Pressure Transducer Using Differential Amplifier.

[BibT_eX]

[DOI]

Pradeep Kumar Rathore

Rangababu Peesapati

Proceedings of the 2018 IEEE SENSORS, New Delhi, India, October 28-31, 2018, 2018

2017

Spaceborne PolSAR Tomography for Forest Height Retrieval.

[BibT_eX]

[DOI]

Sushil Kumar Joshi

Himanshu Govil

IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2017

2016

PCB Defect Classification Using Logical Combination of Segmented Copper and Non-copper Part.

[BibT_eX]

[DOI]

Venkata Karthik Gullapalli

Yuji Iwahori

Manas Kamal Bhuyan

Proceedings of International Conference on Computer Vision and Image Processing, 2016

2015

On Optimizing Human-Machine Task Assignments.

[BibT_eX]

[DOI]

Prithvijit Chakrabarty

Sarveshwaran Dhanasekar

CoRR, 2015

2014

Optimized Power Efficient Routing in Ad-hoc Networks.

[BibT_eX]

[DOI]

Int. J. Next Gener. Comput., 2014

2013

An Efficient Router Architecture and Its FPGA Prototyping to Support Junction Based Routing in NoC Platforms.

[BibT_eX]

[DOI]

Muhammad Awais Aslam

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012

A note on the solution of singular boundary value problems arising in engineering and applied sciences: Use of OHAM.

[BibT_eX]

[DOI]

Mohammad Danish

Surendra Kumar

Comput. Chem. Eng., 2012

Junction based routing: a scalable technique to support source routing in large NoC platforms.

[BibT_eX]

[DOI]

Shabnam Badri

Proceedings of the Fifth International Workshop on Network on Chip Architectures, 2012

2011

Network-on-chip architectures and design methodologies.

[BibT_eX]

[DOI]

Radu Marculescu

Microprocess. Microsystems, 2011

An Abstraction to Support Design of Deadlock-free Routing Algorithms for Large and Hierarchical NoCs.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE International Conference on Computer and Information Technology, 2011

Application-Specific Routing Algorithms for Low Power Network on Chip Design.

[BibT_eX]

[DOI]

Proceedings of the Low Power Networks-on-Chip., 2011

2010

Leveraging Partially Faulty Links Usage for Enhancing Yield and Performance in Networks-on-Chip.

[BibT_eX]

[DOI]

Vincenzo Catania

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

A Multi-level Routing Scheme and Router Architecture to Support Hierarchical Routing in Large Network on Chip Platforms.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2010 Parallel Processing Workshops, 2010

An Efficient Technique for In-order Packet Delivery with Adaptive Routing Algorithms in Networks on Chip.

[BibT_eX]

[DOI]

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Designing Efficient Source Routing for Mesh Topology Network on Chip Platforms.

[BibT_eX]

[DOI]

Saad Mubeen

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009

Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2009

Application Specific Routing Algorithms for Networks on Chip.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2009

Bandwidth-aware routing algorithms for networks-on-chip platforms.

[BibT_eX]

[DOI]

Vincenzo Catania

IET Comput. Digit. Tech., 2009

Enabling web services for Classification of Satellite Image.

[BibT_eX]

Proceedings of the 2009 International Conference on Semantic Web & Web Services, 2009

HiRA: A methodology for deadlock free routing in hierarchical networks on chip.

[BibT_eX]

[DOI]

Proceedings of the Third International Symposium on Networks-on-Chips, 2009

Swarm Intelligence Inspired Classifiers in Comparison with Fuzzy and Rough Classifiers: A Remote Sensing Approach.

[BibT_eX]

[DOI]

Proceedings of the Contemporary Computing - Second International Conference, 2009

Distance Constrained Mapping to Support NoC Platforms Based on Source Routing.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2009, 2009

2008

Deadlock free routing algorithms for irregular mesh topology NoC systems with rectangular regions.

[BibT_eX]

[DOI]

J. Syst. Archit., 2008

Test methods for crosstalk-induced delay and glitch faults in network-on-chip interconnects implementing asynchronous communication protocols.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2008

Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms.

[BibT_eX]

[DOI]

Proceedings of the Second International Symposium on Networks-on-Chips, 2008

Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links.

[BibT_eX]

[DOI]

Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007

Networks-on-Chip: Emerging Research Topics and Novel Ideas.

[BibT_eX]

[DOI]

Davide Bertozzi

VLSI Design, 2007

Corrections to Chen and Chiu's Fault Tolerant Routing Algorithm for Mesh Networks.

[BibT_eX]

[DOI]

J. Inf. Sci. Eng., 2007

Prediction of flow stress for carbon steels using recurrent self-organizing neuro fuzzy networks.

[BibT_eX]

[DOI]

Expert Syst. Appl., 2007

Letter to the Editor.

[BibT_eX]

[DOI]

Comput. Chem. Eng., 2007

Exploiting Communication Concurrency for Efficient Deadlock Free Routing in Reconfigurable NoC Platforms.

[BibT_eX]

[DOI]

Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

2006

Solving Part-Type Selection and Operation Allocation Problems in an FMS: An Approach Using Constraints-Based Fast Simulated Annealing Algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Syst. Man Cybern. Part A, 2006

A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, 2006

Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions.

[BibT_eX]

[DOI]

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Off-Line Testing of Delay Faults in NoC Interconnects.

[BibT_eX]

[DOI]

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

A methodology for design of application specific deadlock-free routing algorithms for NoC systems.

[BibT_eX]

[DOI]

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

2005

Slack-time aware routing in NoC systems.

[BibT_eX]

[DOI]

Daniel Andreasson

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

The Nostrum Backbone - a Communication Protocol Stack for Networks on Chip.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

2003

Hybrid Multi-FPGA Board Evaluation by Permitting Limited Multi-Hop Routing.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2003

Extending Platform-Based Design to Network on Chip Systems.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Modelling and Evaluation of a Network on Chip Architecture Using SDL.

[BibT_eX]

[DOI]

Magnus Högberg

Proceedings of the SDL 2003: System Design, 2003

Algorithms and Tools for Network on Chip Based System Design.

[BibT_eX]

[DOI]

Tang Lei

Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture.

[BibT_eX]

[DOI]

Tang Lei

Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003

On Packet Switched Networks for On-Chip Communication.

[BibT_eX]

[DOI]

Proceedings of the Networks on Chip, 2003

2002

Hybrid Multi-FPGA Board Evaluation by Limiting Multi-Hop Routing.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Workshop on Rapid System Prototyping (RSP 2002), 2002

A Network on Chip Architecture and Design Methodology.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002

Multi-hop routing of multi-terminal nets for evaluation of hybrid multi-FPGA boards.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

2000

A Metamodel for Studying Concepts in Electronic System Design.

[BibT_eX]

[DOI]

Axel Jantsch

Ahmed Hemani

IEEE Des. Test Comput., 2000

Optimal Hardware/Software Partitioning for Concurrent Specification Using Dynamic Programming.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Evaluation of Various Routing Architectures for Multi-FPGA Boards.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Efficient Embedding of Partitioned Circuits onto Multi-FPGA Boards.

[BibT_eX]

[DOI]

Proceedings of the Field-Programmable Logic and Applications, 2000

1999

Globally asynchronous locally synchronous architecture for large high-performance ASICs.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

The Rugby Model: A Conceptual Frame for the Study of Modelling, Analysis and Synthesis Concepts of Electronic Systems.

[BibT_eX]

[DOI]

Axel Jantsch

Ahmed Hemani

Proceedings of the 1999 Design, 1999

Lowering Power Consumption in Clock by Using Globally Asynchronous Locally Synchronous Design Style.

[BibT_eX]

[DOI]

Proceedings of the 36th Conference on Design Automation, 1999

1998

A Methodology and Algorithms for Efficient Interprocess Communication Synthesis from System Description in SDL.

[BibT_eX]

[DOI]

Bengt Svantesson

Ahmed Hemani

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Speeding Up Program Execution Using Reconfigurable Hardware and a Hardware Function Library.

[BibT_eX]

[DOI]

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

1997

Multiobjective Search Based Algorithms for Circuit Partitioning Problem for Acceleration of Logic Simulation.

[BibT_eX]

[DOI]

S. Harikumer

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

A Novel Reconfigurable Co-Processor Architecture.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

1996

Iterative Deepening Multiobjective A.

[BibT_eX]

[DOI]

S. Harikumar

Inf. Process. Lett., 1996

A multiplier generator for Xilinx FPGAs.

[BibT_eX]

[DOI]

Jaswinder Pal Singh

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

1995

An HOL based framework for design of correct high level synthesizers.

[BibT_eX]

[DOI]

B. M. Subraya

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Circuit partitioning with partial order for mixed simulation emulation environment.

[BibT_eX]

[DOI]

Gurmeet Singh Manku

Proceedings of the Sixth IEEE International Workshop on Rapid System Prototyping (RSP '95), 1995

1993

High Level Design Experiences with IDEAS.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Conference on VLSI Design, 1993

1992

A Partitioning Scheme For Multiple Pla Based Control Part Synthesis In Ideas.

[BibT_eX]

[DOI]

Manu Lauria

Proceedings of the Fifth International Conference on VLSI Design, 1992

1991

A heuristic search strategy for optimization of trade-off cost measures.

[BibT_eX]

[DOI]

Rakesh Kumar Singh