Shashank Raghuraman
Orcid: 0000-0001-9355-0527
According to our database1,
Shashank Raghuraman
authored at least 7 papers
between 2017 and 2022.
Collaborative distances:
Collaborative distances:
Timeline
2017
2018
2019
2020
2021
2022
0
1
2
3
4
1
1
1
1
1
2
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2022
Low-Complex and Low-Power n-dimensional Gram-Schmidt Orthogonalization Architecture Design Methodology.
Circuits Syst. Signal Process., 2022
2020
IACR Cryptol. ePrint Arch., 2020
2019
Simplex FastICA: An Accelerated and Low Complex Architecture Design Methodology for $n$ D FastICA.
IEEE Trans. Very Large Scale Integr. Syst., 2019
2018
J. Low Power Electron., 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017
Coordinate rotation and vector cross product based hardware accelerator for nD FastICA.
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017