Sharareh Zamanzadeh
According to our database1,
Sharareh Zamanzadeh
authored at least 10 papers
between 2008 and 2017.
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Bibliography
2017
Scalable security path methodology: A cost-security trade-off to protect FPGA IPs against active and passive tampers.
Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017
2016
Higher security of ASIC fabrication process against reverse engineering attack using automatic netlist encryption methodology.
Microprocess. Microsystems, 2016
ASIC design protection against reverse engineering during the fabrication process using automatic netlist obfuscation design flow.
ISC Int. J. Inf. Secur., 2016
Self authentication path insertion in FPGA-based design flow for tamper-resistant purpose.
ISC Int. J. Inf. Secur., 2016
Security Path: An Emerging Design Methodology to Protect the FPGA IPs Against Passive/Active Design Tampering.
J. Electron. Test., 2016
Security improvement of FPGA configuration file against the reverse engineering attack.
Proceedings of the 13th International Iranian Society of Cryptology Conference on Information Security and Cryptology, 2016
2013
Design, analysis, and implementation of partial product reduction phase by using wide m: 3 (4 ≤ m ≤ 10) compressors.
Int. J. High Perform. Syst. Archit., 2013
Automatic netlist scrambling methodology in ASIC design flow to hinder the reverse engineering.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013
2008
Reimbursing the Handshake Overhead of Asynchronous Circuits using Compiler Pre-Synthesis Optimizations.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
Proceedings of the Advances in Computer Science and Engineering, 2008