Sharad Sinha

According to our database, Sharad Sinha authored at least 69 papers between 2011 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

Combining Weight Approximation, Sharing and Retraining for Neural Network Model Compression.

Prachi Kashikar, Olivier Sentieys, Sharad Sinha

ACM Trans. Embed. Comput. Syst., November, 2024

FADO: Floorplan-Aware Directive Optimization Based on Synthesis and Analytical Models for High-Level Synthesis Designs on Multi-Die FPGAs.

Linfeng Du, Tingyuan Liang, Xiaofeng Zhou, Jinming Ge, Shangkun Li, Sharad Sinha, Jieru Zhao, Zhiyao Xie, Wei Zhang

ACM Trans. Reconfigurable Technol. Syst., September, 2024

AMF-Placer 2.0: Open-Source Timing-Driven Analytical Mixed-Size Placer for Large-Scale Heterogeneous FPGA.

Tingyuan Liang, Gengjie Chen, Jieru Zhao, Sharad Sinha, Wei Zhang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2024

Unveiling the Advantages of Full Coherency Architecture for FPSoC Systems.

Enlai Li, Sharad Sinha, Wei Zhang

IEEE Trans. Very Large Scale Integr. Syst., August, 2024

Lightweight Hardware-Based Cache Side-Channel Attack Detection for Edge Devices (Edge-CaSCADe).

Pavitra Prakash Bhade, Joseph Paturel, Olivier Sentieys, Sharad Sinha

ACM Trans. Embed. Comput. Syst., July, 2024

Shielding against online harm: A survey on text analysis to prevent cyberbullying.

Akanksha Mishra, Sharad Sinha, Clint Pazhayidam George

Eng. Appl. Artif. Intell., 2024

ConvMap: Boosting Convolution Throughput on FPGAs with Efficient Resource Mapping.

Shubhayu Das, Nanditha P. Rao, Sharad Sinha

Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2024

GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection Network.

Chunyou Su, Linfeng Du, Tingyuan Liang, Zhe Lin, Maolin Wang, Sharad Sinha, Wei Zhang

Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2024

2023

Lossless Neural Network Model Compression Through Exponent Sharing.

Prachi Kashikar, Olivier Sentieys, Sharad Sinha

IEEE Trans. Very Large Scale Integr. Syst., November, 2023

HL-Pow: Learning-Assisted Pre-RTL Power Modeling and Optimization for FPGA HLS.

Zhe Lin, Tingyuan Liang, Jieru Zhao, Sharad Sinha, Wei Zhang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

Design and Analysis of RSA and Paillier Homomorphic Cryptosystems Using PSO-Based Evolutionary Computation.

Sathi Sarveswara Reddy, Sharad Sinha, Wei Zhang

IEEE Trans. Computers, July, 2023

AaP-ReID: Improved Attention-Aware Person Re-identification.

Vipin Gautam, Shitala Prasad, Sharad Sinha

CoRR, 2023

Message from Workshop Chairs.

Sheikh K. Ghafoor, Sushil K. Prasad, Ashish Kuvelkar, Sharad Sinha, Satish Puri

Proceedings of the 30th IEEE International Conference on High Performance Computing, 2023

DiffLo: A Graph-based Method for Functional Discrepancy Localization in High-level Synthesis.

Liangji Chen, Tingyuan Liang, Wei Zhang, Sharad Sinha

Proceedings of the International Conference on Field Programmable Technology, 2023

FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs.

Linfeng Du, Tingyuan Liang, Sharad Sinha, Zhiyao Xie, Wei Zhang

Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

Tensor-Product-Based Accelerator for Area-efficient and Scalable Number Theoretic Transform.

Yuying Zhang, Sathi Sarveswara Reddy, Zili Kou, Sharad Sinha, Wei Zhang

Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

Cache Side-channel Attacks and Defenses of the Sliding Window Algorithm in TEEs.

Zili Kou, Sharad Sinha, Wenjian He, Wei Zhang

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Joint-YODNet: A Light-Weight Object Detector for UAVs to Achieve Above 100fps.

Vipin Gautam, Shitala Prasad, Sharad Sinha

Proceedings of the Computer Vision and Image Processing - 8th International Conference, 2023

YOLORe-IDNet: An Efficient Multi-camera System for Person-Tracking.

Vipin Gautam, Shitala Prasad, Sharad Sinha

Proceedings of the Computer Vision and Image Processing - 8th International Conference, 2023

2022

Workings of science: Is engineering applied science?

Sharad Sinha

Ubiquity, 2022

Attack Directories on ARM big.LITTLE Processors.

Zili Kou, Sharad Sinha, Wenjian He, Wei Zhang

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Machine Learning Based Webcasting Analytics for Indian Elections - Reflections on Deployment.

Aditi Saxena, Sharad Sinha

Proceedings of the Computer Vision and Image Processing - 7th International Conference, 2022

2021

Hard-ODT: Hardware-Friendly Online Decision Tree Learning Algorithm and System.

Zhe Lin, Sharad Sinha, Wei Zhang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

A Survey of Algorithmic and Hardware Optimization Techniques for Vision Convolutional Neural Networks on FPGAs.

Arish Sateesan, Sharad Sinha, Smitha K. G., A. P. Vinod

Neural Process. Lett., 2021

Variable Bit-Precision Vector Extension for RISC-V Based Processors.

Risikesh RK, Sharad Sinha, Nanditha P. Rao

Proceedings of the 14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2021

Detection of Cache Side Channel Attacks Using Thread Level Monitoring of Hardware Performance Counters.

Pavitra Prakash Bhade, Sharad Sinha

Proceedings of the 14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2021

Compressing CNNs by Exponent Sharing in Weights using IEEE Single Precision Format.

Prachi Kashikar, Sharad Sinha

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

AMF-Placer: High-Performance Analytical Mixed-size Placer for FPGA.

Tingyuan Liang, Gengjie Chen, Jieru Zhao, Sharad Sinha, Wei Zhang

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Load-Step: A Precise TrustZone Execution Control Framework for Exploring New Side-channel Attacks Like Flush+Evict.

Zili Kou, Wenjian He, Sharad Sinha, Wei Zhang

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Exploiting Weight Statistics for Compressed Neural Network Implementation on Hardware.

Prachi Kashikar, Sharad Sinha, Ajeet Kumar Verma

Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

2020

Optimizing OpenCL-Based CNN Design on FPGA with Comprehensive Design Space Exploration and Collaborative Performance Modeling.

Jiandong Mu, Wei Zhang, Hao Liang, Sharad Sinha

ACM Trans. Reconfigurable Technol. Syst., 2020

Performance Modeling and Directives Optimization for High-Level Synthesis on FPGA.

Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang, Bingsheng He

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

DASH: Design Automation for Synthesis and Hardware Generation for CNN.

Arish Sateesan, Sharad Sinha, Smitha K. G.

Proceedings of the International Conference on Field-Programmable Technology, 2020

FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications.

Jieru Zhao, Tingyuan Liang, Liang Feng, Wenchao Ding, Sharad Sinha, Wei Zhang, Shaojie Shen

Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

iGPU Leak: An Information Leakage Vulnerability on Intel Integrated GPU.

Wenjian He, Wei Zhang, Sharad Sinha, Sanjeev Das

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis.

Zhe Lin, Jieru Zhao, Sharad Sinha, Wei Zhang

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019

An Ensemble Learning Approach for In-Situ Monitoring of FPGA Dynamic Power.

Zhe Lin, Sharad Sinha, Wei Zhang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Artificial intelligence for all using R programming language.

Sharad Sinha, Clint P. George

AI Matters, 2019

Optimization of Convolutional Neural Networks on Resource Constrained Devices.

Arish S, Sharad Sinha, Smitha K. G.

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Smart Nation: Indoor Navigation for the Visually Impaired.

Lim Boon Leng, Smitha K. G., Sharad Sinha

Proceedings of the 4th International Conference on Intelligent Transportation Engineering, 2019

Smart Nation: Offline Public Transport Made Easy.

Ang Poh Keong, K. G. Smitha, Sharad Sinha

Proceedings of the 4th International Conference on Intelligent Transportation Engineering, 2019

Hi-ClockFlow: Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis.

Tingyuan Liang, Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang

Proceedings of the International Conference on Computer-Aided Design, 2019

A Hybrid Data-Consistent Framework for Link-Aware AccessManagement in Emerging CPU-FPGA Platforms.

Liang Feng, Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Towards Efficient and Scalable Acceleration of Online Decision Tree Learning on FPGA.

Zhe Lin, Sharad Sinha, Wei Zhang

Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis.

Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

LAMA: Link-Aware Hybrid Management for Memory Accesses in Emerging CPU-FPGA Platforms.

Liang Feng, Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors.

Zhe Lin, Sharad Sinha, Hao Liang, Liang Feng, Wei Zhang

IEEE Trans. Multi Scale Comput. Syst., 2018

Hi-DMM: High-Performance Dynamic Memory Management in High-Level Synthesis.

Tingyuan Liang, Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Parallelizing Hardware Tasks on Multicontext FPGA With Efficient Placement and Scheduling Algorithms.

Hao Liang, Sharad Sinha, Wei Zhang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

A Collaborative Framework for FPGA-based CNN Design Modeling and Optimization.

Jiandong Mu, Wei Zhang, Hao Liang, Sharad Sinha

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

CAMAS: Static and Dynamic Hybrid Cache Management for CPU-FPGA Platforms.

Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang

Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

2017

HeteroSim: A Heterogeneous CPU-FPGA Simulator.

Liang Feng, Hao Liang, Sharad Sinha, Wei Zhang

IEEE Comput. Archit. Lett., 2017

COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications.

Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang, Bingsheng He

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

A hybrid approach to cache management in heterogeneous CPU-FPGA platforms.

Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Decision tree based hardware power monitoring for run time dynamic power management in FPGA.

Zhe Lin, Wei Zhang, Sharad Sinha

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

PAAS: A system level simulator for heterogeneous computing architectures.

Tingyuan Liang, Liang Feng, Sharad Sinha, Wei Zhang

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2016

Low-Power FPGA Design Using Memoization-Based Approximate Computing.

Sharad Sinha, Wei Zhang

IEEE Trans. Very Large Scale Integr. Syst., 2016

Area Efficient Hardware Architecture for Implicitly-Defined Complex Events Processing.

Mohammad Tahghighi, Wei Zhang, Sharad Sinha

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Analytical Delay Model for CPU-FPGA Data Paths in Programmable System-on-Chip FPGA.

Mohammad Tahghighi, Sharad Sinha, Wei Zhang

Proceedings of the Applied Reconfigurable Computing - 12th International Symposium, 2016

2015

Hierarchical library based power estimator for versatile FPGAs.

Hao Liang, Wei Zhang, Sharad Sinha, Yi-Chung Chen, Hai Li

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Static hardware task placement on multi-context FPGA using hybrid genetic algorithm.

Hao Liang, Sharad Sinha, Rakesh Warrier, Wei Zhang

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

2014

Intelligent high level synthesis for customization on reconfigurable platforms

Sharad Sinha

PhD thesis, 2014

Dataflow Graph Partitioning for Area-Efficient High-Level Synthesis with Systems Perspective.

Sharad Sinha, Thambipillai Srikanthan

ACM Trans. Design Autom. Electr. Syst., 2014

Extended Compatibility Path Based Hardware binding: an Adaptive Algorithm for High Level synthesis of Area-Time Efficient Designs.

Sharad Sinha, Udit Dhawan, Thambipillai Srikanthan

J. Circuits Syst. Comput., 2014

Architecture and Application-Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level Synthesis.

Sharad Sinha, Thambipillai Srikanthan

Int. J. Reconfigurable Comput., 2014

IP-Enabled C/C++ Based High Level Synthesis: A Step towards Better Designer Productivity and Design Performance.

Sharad Sinha, Thambipillai Srikanthan

Int. J. Reconfigurable Comput., 2014

A Bit-Level Block Cipher Diffusion Analysis Test - BLDAT.

Dipanjan Bhowmik, Avijit Datta, Sharad Sinha

Proceedings of the 3rd International Conference on Frontiers of Intelligent Computing: Theory and Applications (FICTA) 2014, 2014

2012

Dataflow graph partitioning for high level synthesis.

Sharad Sinha, Thambipillai Srikanthan

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

2011

A Novel Binding Algorithm to Reduce Critical Path Delay During High Level Synthesis.

Sharad Sinha, Udit Dhawan, Siew Kei Lam, Thambipillai Srikanthan

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011