Sharad Malik

Proceedings of the Hardware and Software: Verification and Testing, 2017

Solving linear arithmetic with SAT-based model checking.

[BibT_eX]

[DOI]

Alexander Nadel

Proceedings of the 2017 Formal Methods in Computer Aided Design, 2017

Malware detection using machine learning based analysis of virtual memory access patterns.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Evaluating matrix representations for error-tolerant computing.

[BibT_eX]

[DOI]

Pareesa Ameneh Golnari

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

Model checking unbounded concurrent lists.

[BibT_eX]

[DOI]

Muralidhar Talupur

Int. J. Softw. Tools Technol. Transf., 2016

On computing minimal independent support and its applications to sampling and counting.

[BibT_eX]

[DOI]

Constraints An Int. J., 2016

Verifying information flow properties of firmware using symbolic execution.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Invited - Specification and modeling for systems-on-chip security verification.

[BibT_eX]

[DOI]

Pramod Subramanyan

Proceedings of the 53rd Annual Design Automation Conference, 2016

Constrained Sampling and Counting: Universal Hashing Meets SAT Solving.

[BibT_eX]

[DOI]

Proceedings of the Beyond NP, 2016

2015

Boolean Satisfiability Solvers and Their Applications in Model Checking.

[BibT_eX]

[DOI]

Proc. IEEE, 2015

Error-Tolerant Processors: Formal Specification and Verification.

[BibT_eX]

[DOI]

Ameneh Golnari

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Evaluating the security of logic encryption algorithms.

[BibT_eX]

[DOI]

Pramod Subramanyan

Sayak Ray

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

Template-based Synthesis of Instruction-Level Abstractions for SoC Verification.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods in Computer-Aided Design, 2015

Detecting Hardware Trojans: A Tale of Two Techniques.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods in Computer-Aided Design, 2015

Optimizing dynamic trace signal selection using machine learning and linear programming.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Hardware Trojan detection for gate-level ICs using signal correlation based clustering.

[BibT_eX]

[DOI]

Burçin Çakir

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Completeness bounds and sequentialization for model checking of interacting firmware and hardware.

[BibT_eX]

[DOI]

Sunha Ahn

Proceedings of the 2015 International Conference on Hardware/Software Codesign and System Synthesis, 2015

Fast Interpolating BMC.

[BibT_eX]

[DOI]

Arie Gurfinkel

Proceedings of the Computer Aided Verification - 27th International Conference, 2015

CommGuard: Mitigating Communication Errors in Error-Prone Parallel Execution.

[BibT_eX]

[DOI]

Yavuz Yetim

Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, 2015

2014

Boolean Satisfiability: Solvers and Extensions.

[BibT_eX]

[DOI]

Pramod Subramanyan

Proceedings of the Software Systems Safety, 2014

Reverse Engineering Digital Circuits Using Structural and Functional Analyses.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2014

All-SAT Using Minimal Blocking Clauses.

[BibT_eX]

[DOI]

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

An assertion language for debugging SDN applications.

[BibT_eX]

[DOI]

Proceedings of the third workshop on Hot topics in software defined networking, 2014

Effective abstraction for response proof of communication fabrics.

[BibT_eX]

[DOI]

Sayak Ray

Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

In-Band Update for Network Routing Policy Migration.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Conference on Network Protocols, 2014

Silicon fault diagnosis using sequence interpolation with backbones.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Reduction of Resolution Refutations and Interpolants via Subsumption.

[BibT_eX]

[DOI]

Proceedings of the Hardware and Software: Verification and Testing, 2014

Template-based circuit understanding.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods in Computer-Aided Design, 2014

An Adaptable Rule Placement for Software-Defined Networks.

[BibT_eX]

[DOI]

Proceedings of the 44th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2014

Automated firmware testing using firmware-hardware interaction patterns.

[BibT_eX]

[DOI]

Sunha Ahn

Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

Using Flow Specifications of Parameterized Cache Coherence Protocols for Verifying Deadlock Freedom.

[BibT_eX]

[DOI]

Muralidhar Talupur

Proceedings of the Automated Technology for Verification and Analysis, 2014

2013

Modeling Firmware as Service Functions and Its Application to Test Generation.

[BibT_eX]

[DOI]

Sunha Ahn

Proceedings of the Hardware and Software: Verification and Testing, 2013

WordRev: Finding word-level structures in a sea of bit-level gates.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, 2013

Abstractions for model checking SDN controllers.

[BibT_eX]

[DOI]

Srinivas Narayana

Proceedings of the Formal Methods in Computer-Aided Design, 2013

Extracting useful computation from error-prone processors for streaming applications.

[BibT_eX]

[DOI]

Yavuz Yetim

Proceedings of the Design, Automation and Test in Europe, 2013

Reverse engineering digital circuits using functional analysis.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

SAT Based Verification of Network Data Planes.

[BibT_eX]

[DOI]

Shuyuan Zhang

Proceedings of the Automated Technology for Verification and Analysis, 2013

2012

Boolean Satisfiability Solvers: Techniques and Extensions.

[BibT_eX]

[DOI]

Proceedings of the Software Safety and Security - Tools for Analysis and Verification, 2012

Wolverine: Battling Bugs with Interpolants - (Competition Contribution).

[BibT_eX]

[DOI]

Daniel Kroening

Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2012

Parameterized Model Checking of Fine Grained Concurrency.

[BibT_eX]

[DOI]

Muralidhar Talupur

Proceedings of the Model Checking Software - 19th International Workshop, 2012

Verification and synthesis of firewalls using SAT and QBF.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Conference on Network Protocols, 2012

Coverage-Based Trace Signal Selection for Fault Localisation in Post-silicon Validation.

[BibT_eX]

[DOI]

Proceedings of the Hardware and Software: Verification and Testing, 2012

Efficient predictive analysis for detecting nondeterminism in multi-threaded programs.

[BibT_eX]

[DOI]

Arnab Sinha

Proceedings of the Formal Methods in Computer-Aided Design, 2012

Specification and synthesis of hardware checkpointing and rollback mechanisms.

[BibT_eX]

[DOI]

Carven Chan

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

passert: A Tool for Debugging Parallel Programs.

[BibT_eX]

[DOI]

Feng Liu

David I. August

Proceedings of the Computer Aided Verification - 24th International Conference, 2012

Verification of Computer Switching Networks: An Overview.

[BibT_eX]

[DOI]

Shuyuan Zhang

Rick McGeer

Proceedings of the Automated Technology for Verification and Analysis, 2012

Parallel Assertions for Architectures with Weak Memory Models.

[BibT_eX]

[DOI]

Proceedings of the Automated Technology for Verification and Analysis, 2012

EPROF: An energy/performance/reliability optimization framework for streaming applications.

[BibT_eX]

[DOI]

Yavuz Yetim

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Specification and encoding of transaction interaction properties.

[BibT_eX]

[DOI]

Formal Methods Syst. Des., 2011

Towards Eliminating Configuration Errors in Cyber Infrastructure.

[BibT_eX]

[DOI]

Sanjai Narain

Ehab Al-Shaer

Proceedings of the 4th Symposium on Configuration Analytics and Automation, SafeConfig 2011, Arlington, VA, USA, October 31, 2011

Runtime Verification: A Computer Architecture Perspective.

[BibT_eX]

[DOI]

Proceedings of the Runtime Verification - Second International Conference, 2011

Predictive analysis for detecting serializability violations through Trace Segmentation.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE/ACM International Conference on Formal Methods and Models for Codesign, 2011

Parallel assertions for debugging parallel programs.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE/ACM International Conference on Formal Methods and Models for Codesign, 2011

Predicting Serializability Violations: SMT-Based Search vs. DPOR-Based Search.

[BibT_eX]

[DOI]

Proceedings of the Hardware and Software: Verification and Testing, 2011

SAT-based techniques for determining backbones for post-silicon fault localisation.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011

Post-silicon fault localisation using maximum satisfiability and backbones.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Formal Methods in Computer-Aided Design, 2011

2010

Runtime checking of serializability in software transactional memory.

[BibT_eX]

[DOI]

Arnab Sinha

Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Utility of transaction-level hardware models in refinement checking.

[BibT_eX]

[DOI]

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

2009

Conflict-Driven Clause Learning SAT Solvers.

[BibT_eX]

[DOI]

João Marques-Silva

Inês Lynce

Proceedings of the Handbook of Satisfiability, 2009

Preface.

[BibT_eX]

[DOI]

Formal Methods Syst. Des., 2009

Boolean satisfiability from theoretical hardness to practical success.

[BibT_eX]

[DOI]

Commun. ACM, 2009

Supporting RTL flow compatibility in a microarchitecture-level design framework.

[BibT_eX]

[DOI]

Carven Chan

Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

2008

Declarative Infrastructure Configuration Synthesis and Debugging.

[BibT_eX]

[DOI]

J. Netw. Syst. Manag., 2008

Challenges and Solutions for Late- and Post-Silicon Design.

[BibT_eX]

[DOI]

Jan M. Rabaey

IEEE Des. Test Comput., 2008

Exploiting Circuit Reconvergence through Static Learning in CNF SAT Solvers.

[BibT_eX]

[DOI]

Cameron Brien

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Hardware Verification: Techniques, Methodology and Solutions.

[BibT_eX]

[DOI]

Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2008

Runtime Validation of Transactional Memory Systems.

[BibT_eX]

[DOI]

Priyadarsan Patra

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Runtime validation of memory ordering using constraint graph checking.

[BibT_eX]

[DOI]

Priyadarsan Patra

Proceedings of the 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 2008

2007

A hierarchical modeling framework for on-chip communication architectures of multiprocessing SoCs.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2007

Extracting Logic Circuit Structure from Conjunctive Normal Form Descriptions.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Verification Driven Formal Architecture and Microarchitecture Modeling.

[BibT_eX]

[DOI]

Proceedings of the 5th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2007), May 30, 2007

Automating Hazard Checking in Transaction-Level Microarchitecture Models.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods in Computer-Aided Design, 7th International Conference, 2007

A Retargetable Very Long Instruction Word Compiler Framework for Digital Signal Processors.

[BibT_eX]

Proceedings of the Compiler Design Handbook: Optimizations and Machine Code Generation, 2007

Architecture Description Languages for Retargetable Compilation.

[BibT_eX]

Proceedings of the Compiler Design Handbook: Optimizations and Machine Code Generation, 2007

2006

Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

The Liberty Simulation Environment: A deliberate approach to high-level system modeling.

[BibT_eX]

[DOI]

ACM Trans. Comput. Syst., 2006

Lemma Learning in SMT on Linear Constraints.

[BibT_eX]

[DOI]

Proceedings of the Theory and Applications of Satisfiability Testing, 2006

Solving Quantified Boolean Formulas with Circuit Observability Don't Cares.

[BibT_eX]

[DOI]

Daijue Tang

Proceedings of the Theory and Applications of Satisfiability Testing, 2006

On Solving the Partial MAX-SAT Problem.

[BibT_eX]

[DOI]

Proceedings of the Theory and Applications of Satisfiability Testing, 2006

Dependable Multithreaded Processing Using Runtime Validation.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2006), 2006

Solving the minimum-cost satisfiability problem using SAT based branch-and-bound search.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Understanding the Dynamic Behavior of Modern DPLL SAT Solvers through Visual Analysis.

[BibT_eX]

[DOI]

Cameron Brien

Proceedings of the Formal Methods in Computer-Aided Design, 6th International Conference, 2006

2005

Achieving Structural and Composable Modeling of Complex Systems.

[BibT_eX]

[DOI]

Int. J. Parallel Program., 2005

A Study of Architecture Description Languages from a Model-based Perspective.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005

Bounds on power savings using runtime dynamic voltage scaling: an exact algorithm and a linear-time heuristic approximation.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Complementary use of runtime validation and model checking.

[BibT_eX]

[DOI]

Ali Alphan Bayazit

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

A Case for Runtime Validation of Hardware.

[BibT_eX]

[DOI]

Proceedings of the Hardware and Software Verification and Testing, 2005

A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks.

[BibT_eX]

[DOI]

Hangsheng Wang

Li-Shiuan Peh

Proceedings of the 2005 Design, 2005

Considering Circuit Observability Don't Cares in CNF Satisfiability.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

Efficient behavior-driven runtime dynamic voltage scaling policies.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

Symmetry Reduction in SAT-Based Model Checking.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification, 17th International Conference, 2005

Validating the result of a Quantified Boolean Formula (QBF) solver: theory and practice.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

The design of dynamically reconfigurable datapath coprocessors.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2004

Intraprogram dynamic voltage scaling: Bounding opportunities with analytic modeling.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2004

Guest Editors' Introduction: Exploring Synergies for Design Verification.

[BibT_eX]

[DOI]

Carl Pixley

IEEE Des. Test Comput., 2004

Analysis of Search Based Algorithms for Satisfiability of Propositional and Quantified Boolean Formulas Arising from Circuit State Space Diameter Problems.

[BibT_eX]

[DOI]

Proceedings of the Theory and Applications of Satisfiability Testing, 2004

Analysis of Search Based Algorithms for Satisfiability of Quantified Boolean Formulas Arising from Circuit State Space Diameter Problems.

[BibT_eX]

[DOI]

Proceedings of the SAT 2004, 2004

A Comparative Study of 2QBF Algorithms.

[BibT_eX]

[DOI]

Darsh Ranjan

Daijue Tang

Proceedings of the SAT 2004, 2004

Zchaff2004: An Efficient SAT Solver.

[BibT_eX]

[DOI]

Proceedings of the Theory and Applications of Satisfiability Testing, 2004

A formal concurrency model based architecture description language for synthesis of software development tools.

[BibT_eX]

[DOI]

Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, 2004

Achieving Structural and Composable Modeling of Complex Systems.

[BibT_eX]

[DOI]

Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

Using a Communication Architecture Specification in an Application-Driven Retargetable Prototyping Platform for Multiprocessing.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

Facilitating reuse in hardware models with enhanced type inference.

[BibT_eX]

[DOI]

Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

2003

A Power Model for Routers: Modeling Alpha 21364 and InfiniBand Routers.

[BibT_eX]

[DOI]

Hangsheng Wang

Li-Shiuan Peh

IEEE Micro, 2003

Cache Performance of SAT Solvers: a Case Study for Efficient Implementation of Algorithms.

[BibT_eX]

[DOI]

Proceedings of the Theory and Applications of Satisfiability Testing, 2003

Compile-time dynamic voltage scaling settings: opportunities and limits.

[BibT_eX]

[DOI]

Proceedings of the ACM SIGPLAN 2003 Conference on Programming Language Design and Implementation 2003, 2003

Power-driven Design of Router Microarchitectures in On-chip Networks.

[BibT_eX]

[DOI]

Hangsheng Wang

Li-Shiuan Peh

Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003

Validating SAT Solvers Using an Independent Resolution-Based Checker: Practical Implementations and Other Applications.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

Modeling and Integration of Peripheral Devices in Embedded Systems.

[BibT_eX]

[DOI]

Shaojie Wang

Reinaldo A. Bergamaschi

Proceedings of the 2003 Design, 2003

Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

Automated synthesis of efficient binary decoders for retargetable software toolkits.

[BibT_eX]

[DOI]

Proceedings of the 40th Design Automation Conference, 2003

Synthesizing operating system based device drivers in embedded systems.

[BibT_eX]

[DOI]

Shaojie Wang

Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

Modeling and Integration of Peripheral Devices in Embedded Systems.

[BibT_eX]

[DOI]

Shaojie Wang

Reinaldo A. Bergamaschi

Proceedings of the Embedded Software for SoC, 2003

2002

Limits of Using Signatures for Permutation Independent Boolean Comparison.

[BibT_eX]

[DOI]

Paul Molitor

Formal Methods Syst. Des., 2002

Developing Architectural Platforms: A Disciplined Approach.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2002

Orion: a power-performance simulator for interconnection networks.

[BibT_eX]

[DOI]

Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

Datapath Merging and Interconnection Sharing for Reconfigurable Architectures.

[BibT_eX]

[DOI]

Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

From ASIC to ASIP: The Next Design Discontinuity.

[BibT_eX]

[DOI]

A. Richard Newton

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

A hierarchical modeling framework for on-chip communication architectures.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Conflict driven learning in a quantified Boolean Satisfiability solver.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Design Tools for Application Specific Embedded Processors.

[BibT_eX]

[DOI]

Proceedings of the Embedded Software, Second International Conference, 2002

Unified tools for SoC embedded systems: mission critical, mission impossible or mission irrelevant?

[BibT_eX]

[DOI]

Proceedings of the 39th Design Automation Conference, 2002

Exploiting operation level parallelism through dynamically reconfigurable datapaths.

[BibT_eX]

[DOI]

Zhining Huang

Proceedings of the 39th Design Automation Conference, 2002

Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver.

[BibT_eX]

[DOI]

Proceedings of the 39th Design Automation Conference, 2002

Towards a Symmetric Treatment of Satisfaction and Conflicts in Quantified Boolean Formula Evaluation.

[BibT_eX]

[DOI]

Proceedings of the Principles and Practice of Constraint Programming, 2002

The Quest for Efficient Boolean Satisfiability Solvers.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification, 14th International Conference, 2002

Retargetable Very Long Instuction Word Compiler Framework for Digital Signal Processors.

[BibT_eX]

[DOI]

Proceedings of the Compiler Design Handbook: Optimizations and Machine Code Generation, 2002

Architecture Description Languages for Retargetable Compilation.

[BibT_eX]

[DOI]

Proceedings of the Compiler Design Handbook: Optimizations and Machine Code Generation, 2002

2001

Using complete-1-distinguishability for FSM equivalence checking.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2001

A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Application of BDDs in Boolean matching techniques for formal logic combinational verification.

[BibT_eX]

[DOI]

Paul Molitor

Int. J. Softw. Tools Technol. Transf., 2001

Accelerating boolean satisfiability through application specific processing.

[BibT_eX]

[DOI]

Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Retargetable static timing analysis for embedded software.

[BibT_eX]

[DOI]

David I. August

Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Matching Architecture to Application Via Configurable Processors: A Case Study with Boolean Satisfiability Problem.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

Efficient Conflict Driven Learning in Boolean Satisfiability Solver.

[BibT_eX]

[DOI]

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Partition-Based Decision Heuristics for Image Computation Using SAT and BDDs.

[BibT_eX]

[DOI]

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Embedded Software Implementation Tools for Fully Programmable Application Specific Systems.

[BibT_eX]

[DOI]

Proceedings of the Embedded Software, First International Workshop, 2001

Managing dynamic reconfiguration overhead in systems-on-a-chip design using reconfigurable datapaths and optimized interconnection networks.

[BibT_eX]

[DOI]

Zhining Huang

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design.

[BibT_eX]

[DOI]

Proceedings of the 38th Design Automation Conference, 2001

Chaff: Engineering an Efficient SAT Solver.

[BibT_eX]

[DOI]

Proceedings of the 38th Design Automation Conference, 2001

Optimal Live Range Merge for Address Register Allocation in Embedded Programs.

[BibT_eX]

[DOI]

Guilherme Ottoni

Sandro Rigo

Proceedings of the Compiler Construction, 10th International Conference, 2001

2000

Exact memory size estimation for array computations.

[BibT_eX]

[DOI]

Ying Zhao

IEEE Trans. Very Large Scale Integr. Syst., 2000

Simultaneous reference allocation in code generation for dual data memory bank ASIPs.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2000

Processor Evaluation in an Embedded Systems Design Environment.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Automated cache optimizations using CME driven diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 14th international conference on Supercomputing, 2000

Incremental CAD.

[BibT_eX]

[DOI]

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Embedded systems education (panel abstract).

[BibT_eX]

[DOI]

Wayne H. Wolf

Proceedings of the 37th Conference on Design Automation, 2000

Handling irregular ILP within conventional VLIW schedulers using artificial resource constraints.

[BibT_eX]

[DOI]

Manish Vachharajani

Proceedings of the 2000 International Conference on Compilers, 2000

1999

Cache miss equations: a compiler framework for analyzing and tuning memory behavior.

[BibT_eX]

[DOI]

ACM Trans. Program. Lang. Syst., 1999

Performance estimation of embedded software with instruction cache modeling.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 1999

Using configurable computing to accelerate Boolean satisfiability.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Establishing latch correspondence for sequential circuits using distinguishing signatures.

[BibT_eX]

[DOI]

Paul Molitor

Integr., 1999

Paged Absolute Addressing Mode Optimizations for Embedded Digital Signal Processors Using Post-pass Data-flow Analysis.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 1999

A Retargetable Compilation Methodology for Embedded Digital Signal Processors Using a Machine-Dependent Code Optimization Library.

[BibT_eX]

[DOI]

Masahiro Fujita

Des. Autom. Embed. Syst., 1999

CAD Techniques for Embedded System Design.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Exact Memory Size Estimation for Array Computations without Loop Unrolling.

[BibT_eX]

[DOI]

Ying Zhao

Proceedings of the 36th Conference on Design Automation, 1999

Development of an optimizing compiler for a Fujitsu fixed-point digital signal processor.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

Exploiting Retiming in a Guided Simulation Based Validation Methodology.

[BibT_eX]

[DOI]

Proceedings of the Correct Hardware Design and Verification Methods, 1999

Performance analysis of real-time embedded software.

[BibT_eX]

Springer, ISBN: 978-0-7923-8382-6, 1999

1998

Code generation for fixed-point DSPs.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 1998

Guarded evaluation: pushing power management to logic synthesis/design.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Solving Boolean Satisfiability with Dynamic Hardware Configurations.

[BibT_eX]

[DOI]

Proceedings of the Field-Programmable Logic and Applications, 1998

Accelerating Boolean Satisfiability with Configurable Hardware.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998

Using Reconfigurable Computing Techniques to Accelerate Problems in the CAD Domain: A Case Study with Boolean Satisfiability.

[BibT_eX]

[DOI]

Proceedings of the 35th Conference on Design Automation, 1998

Precise Miss Analysis for Program Transformations with Caches of Arbitrary Associativity.

[BibT_eX]

[DOI]

Proceedings of the ASPLOS-VIII Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, 1998

1997

Power analysis and minimization techniques for embedded DSP software.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1997

Performance analysis of embedded software using implicit path enumeration.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Delay abstraction in combinational logic circuits.

[BibT_eX]

[DOI]

Noriya Kobayashi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Dynamic Power Management for Microprocessors: A Case Study.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Cache Miss Equations: An Analytical Representation of Cache Misses.

[BibT_eX]

[DOI]

Proceedings of the 11th international conference on Supercomputing, 1997

Optimization of embedded DSP programs using post-pass data-flow analysis.

[BibT_eX]

[DOI]

Proceedings of the 1997 IEEE International Conference on Acoustics, 1997

Cinderella: A Retargetable Environment for Performance Analysis of Real-Time Software.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par '97 Parallel Processing, 1997

Static Timing Analysis of Embedded Software.

[BibT_eX]

[DOI]

Proceedings of the 34st Conference on Design Automation, 1997

Toward Formalizing a Validation Methodology Using Simulation Coverage.

[BibT_eX]

[DOI]

Proceedings of the 34st Conference on Design Automation, 1997

1996

Instruction level power analysis and optimization of software.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 1996

Technology mapping for low power in logic synthesis.

[BibT_eX]

[DOI]

Integr., 1996

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Cache modeling for real-time software: beyond direct mapped instruction caches.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE Real-Time Systems Symposium (RTSS '96), 1996

Instruction Set Design and Optimizations for Address Computation in DSP Architectures.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on System Synthesis, 1996

The case for retiming with explicit reset circuitry.

[BibT_eX]

[DOI]

Vigyan Singhal

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Using Register-Transfer Paths in Code Generation for Heterogeneous Memory-Register Architectures.

[BibT_eX]

[DOI]

Mike Tien-Chien Lee

Proceedings of the 33st Conference on Design Automation, 1996

1995

Test generation for cyclic combinational circuits.

[BibT_eX]

[DOI]

Anand Raghunathan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Functional timing analysis using ATPG.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Exploiting multicycle false paths in the performance optimization of sequential logic circuits.

[BibT_eX]

[DOI]

Sujit Dey

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Multisensor Integration for Underwater Scene Classification.

[BibT_eX]

[DOI]

N. Nandhakumar

Appl. Intell., 1995

Efficient Microarchitecture Modeling and Path Analysis for Real-Time Software.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE Real-Time Systems Symposium, 1995

Power analysis and low-power scheduling techniques for embedded DSP software.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), 1995

Optimal code generation for embedded memory non-homogeneous register architectures.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), 1995

Memory bank and register allocation in software synthesis for ASIPs.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Fast functional simulation using branching programs.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Prediction of interconnect delay in logic synthesis.

[BibT_eX]

[DOI]

Horng-Fei Jyu

Proceedings of the 1995 European Design and Test Conference, 1995

A Survey of Optimization Techniques Targeting Low Power VLSI Circuits.

[BibT_eX]

[DOI]

Proceedings of the 32st Conference on Design Automation, 1995

1994

Editorial.

[BibT_eX]

[DOI]

Teresa H. Meng

J. VLSI Signal Process., 1994

Verification of asynchronous interface circuits with bounded wire delays.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 1994

Power analysis of embedded software: a first step towards software power minimization.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1994

Certified timing verification and the transition delay of a logic circuit.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1994

Analysis of cyclic combinational circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Event suppression: improving the efficiency of timing simulation for synchronous digital circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Challenges in code generation for embedded processors.

[BibT_eX]

Proceedings of the Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31, 1994

Statistical Delay Modeling in Logic Design and Synthesis.

[BibT_eX]

[DOI]

Horng-Fei Jyu

Proceedings of the 31st Conference on Design Automation, 1994

Implicit Computation of Minimum-Cost Feedback-Vertex Sets for Partial Scan and Other Applications.

[BibT_eX]

[DOI]

Proceedings of the 31st Conference on Design Automation, 1994

1993

Statistical timing analysis of combinational logic circuits.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1993

Performance optimization of pipelined logic circuits using peripheral retiming and resynthesis.

[BibT_eX]

[DOI]

Kanwar Jit Singh

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Computation of floating mode delay in combinational circuits: practice and implementation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Computation of floating mode delay in combinational circuits: theory and algorithms.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Permutation and phase independent Boolean comparison.

[BibT_eX]

[DOI]

Integr., 1993

A synthesis-based test generation and compaction algorithm for multifaults.

[BibT_eX]

[DOI]

J. Electron. Test., 1993

Statistical Timing Optimization of Combinatorial Logic Circuits.

[BibT_eX]

[DOI]

Horng-Fei Jyu

Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Technology Mapping for Lower Power.

[BibT_eX]

[DOI]

Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992

Symbolic minimization of multilevel logic and the input encoding problem.

[BibT_eX]

[DOI]

Luciano Lavagno

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Statistical Timing Analysis of Combinational Circuits.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

Exploiting multi-cycle false paths in the performance optimization of sequential circuits.

[BibT_eX]

[DOI]

Sujit Dey

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

1991

Retiming and resynthesis: optimizing sequential networks with combinational techniques.

[BibT_eX]

[DOI]

Ellen M. Sentovich

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Is redundancy necessary to reduce delay?

[BibT_eX]

[DOI]

Alexander Saldanha

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Delay Computation in Combinational Logic Circuits: Theory and Algorithms.

[BibT_eX]

[DOI]

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

1990

Algorithms for Discrete Function Manipulation.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Performance Optimization of Pipelined Circuits.

[BibT_eX]

[DOI]

Kanwar Jit Singh

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

MIS-MV: Optimization of Multi-Level Logic with Multiple-Valued Inputs.

[BibT_eX]

[DOI]

Luciano Lavagno

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

1988

Logic verification using binary decision diagrams in a logic synthesis environment.

[BibT_eX]

[DOI]

Albert R. Wang