Sharad C. Seth

Proceedings of the Encyclopedia of GIS., 2017

Feature Extraction, Abstract.

[BibT_eX]

[DOI]

Proceedings of the Encyclopedia of GIS., 2017

Energy-efficient I/O Thread Schedulers for NVMe SSDs on NUMA.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE/ACM International Symposium on Cluster, 2017

2016

Converting heterogeneous statistical tables on the web to searchable databases.

[BibT_eX]

[DOI]

Int. J. Document Anal. Recognit., 2016

Exploiting FIFO Scheduler to Improve Parallel Garbage Collection Performance.

[BibT_eX]

[DOI]

Proceedings of the 12th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, 2016

Table headers: An entrance to the data mine.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Pattern Recognition, 2016

2015

SmartStealing: Analysis and Optimization of Work Stealing in Parallel Garbage Collection for Java VM.

[BibT_eX]

[DOI]

Proceedings of the Principles and Practices of Programming on The Java Platform, 2015

Factors affecting scalability of multithreaded Java applications on manycore systems.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Performance Analysis of Systems and Software, 2015

Clustering header categories extracted from web tables.

[BibT_eX]

[DOI]

Proceedings of the Document Recognition and Retrieval XXII, 2015

2014

CLU: Co-Optimizing Locality and Utility in Thread-Aware Capacity Management for Shared Last Level Caches.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2014

Transforming Web Tables to a Relational Database.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Pattern Recognition, 2014

End-to-End Conversion of HTML Tables for Populating a Relational Database.

[BibT_eX]

[DOI]

Proceedings of the 11th IAPR International Workshop on Document Analysis Systems, 2014

2013

Segmenting Tables via Indexing of Value Cells by Table Headers.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on Document Analysis and Recognition, 2013

2012

Locality & utility co-optimization for practical capacity management of shared last level caches.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Supercomputing, 2012

2011

Factoring Web Tables.

[BibT_eX]

[DOI]

Proceedings of the Modern Approaches in Applied Intelligence, 2011

Data Extraction from Web Tables: The Devil is in the Details.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Document Analysis and Recognition, 2011

Diagnosis of Multiple Scan-Chain Faults in the Presence of System Logic Defects.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

PVT: Unified Reduction of Test Power, Volume, and Test Time Using Double-Tree Scan Architecture.

[BibT_eX]

[DOI]

J. Low Power Electron., 2010

A novel hybrid delay testing scheme with low test power, volume, and time.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

A Unified Solution to Scan Test Volume, Time, and Power Minimization.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

STEM: Spatiotemporal Management of Capacity for Intra-core Last Level Caches.

[BibT_eX]

[DOI]

Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

Hardware implementation of the double-tree scan architecture.

[BibT_eX]

[DOI]

Nathan Schemm

Sina Balkir

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Exploiting set-level non-uniformity of capacity demand to enhance CMP cooperative caching.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Analysis and taxonomy of column header categories for web tables.

[BibT_eX]

[DOI]

Ramana Chakradhar Jandhyala

Proceedings of the Ninth IAPR International Workshop on Document Analysis Systems, 2010

2009

Comment: Projection Methods Require Black Border Removal.

[BibT_eX]

[DOI]

Ramana Chakradhar Jandhyala

Mahesh Viswanathan

IEEE Trans. Pattern Anal. Mach. Intell., 2009

From Tessellations to Table Interpretation.

[BibT_eX]

[DOI]

Raghav K. Padmanabhan

Raghav Krishna Padmanabhan

William Silversmith

Proceedings of the Intelligent Computer Mathematics, 2009

Interactive Conversion of Web Tables.

[BibT_eX]

[DOI]

Ramana Chakradhar Jandhyala

William Silversmith

Proceedings of the Graphics Recognition. Achievements, 2009

2008

Conflation of Features.

[BibT_eX]

[DOI]

Proceedings of the Encyclopedia of GIS., 2008

Feature Extraction, Abstract.

[BibT_eX]

[DOI]

Proceedings of the Encyclopedia of GIS., 2008

Planar Straight-Line Embedding of Double-Tree Scan Architecture on a Rectangular Grid.

[BibT_eX]

[DOI]

Indranil Saha

Fundam. Informaticae, 2008

Efficient Selection of Observation Points for Functional Tests.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2007

Efficient RTL Coverage Metric for Functional Test Selection.

[BibT_eX]

[DOI]

Jian Kang

Vijay Gangaram

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Symbolic Path Sensitization Analysis and Applications.

[BibT_eX]

[DOI]

Jian Kang

Proceedings of the 16th Asian Test Symposium, 2007

2006

Multi-character Field Recognition for Arabic and Chinese Handwriting.

[BibT_eX]

[DOI]

Proceedings of the Arabic and Chinese Handwriting Recognition, 2006

A Maximum-Likelihood Approach to Symbolic Indirect Correlation.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on Pattern Recognition (ICPR 2006), 2006

2005

On Finding Consecutive Test Vectors in a Random Sequence for Energy-Aware BIST Design.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Efficient Test Compaction for Pseudo-Random Testing.

[BibT_eX]

[DOI]

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

A feature-based approach to conflation of geospatial sources.

[BibT_eX]

[DOI]

Kevin Cueto

Int. J. Geogr. Inf. Sci., 2004

A nonparametric classifier for unsegmented text.

[BibT_eX]

[DOI]

Ashutosh Joshi

Proceedings of the Document Recognition and Retrieval XI, 2004

2003

Modeling Fault Coverage of Random Test Patterns.

[BibT_eX]

[DOI]

Hailong Cui

J. Electron. Test., 2003

Low-Energy BIST Design for Scan-based Logic Circuits.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Double-Tree Scan: A Novel Low-Power Scan-Path Architecture.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Indirect Symbolic Correlation Approach to Unsegmented Text Recognition.

[BibT_eX]

[DOI]

Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2003

2002

A Novel Method to Improve the Test Efficiency of VLSI Tests.

[BibT_eX]

[DOI]

Hailong Cui

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

2001

Design Verification and Functional Testing of FiniteState Machines.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Adaptive Segmentation of Document Images.

[BibT_eX]

[DOI]

Don Sylwester

Proceedings of the 6th International Conference on Document Analysis and Recognition (ICDAR 2001), 2001

2000

Integrated text and line-art extraction from a topographic map.

[BibT_eX]

[DOI]

Int. J. Document Anal. Recognit., 2000

Exploiting don't cares to enhance functional tests.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

1999

A synthesis for testability scheme for finite state machines using clock control.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Empirical Computation of Reject Ratio in VLSI Testing.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Cooperative Text and Line-Art Extraction from a Topographic Map.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Conference on Document Analysis and Recognition, 1999

1998

Mutually Disjoint Signals and Probability Calculation in Digital Circuits.

[BibT_eX]

[DOI]

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

Synthesis of Sequential Circuits with Clock Control to Improve Testability.

[BibT_eX]

[DOI]

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997

A system for recognizing a large class of engineering drawings.

[BibT_eX]

[DOI]

Yuhong Yu

IEEE Trans. Pattern Anal. Mach. Intell., 1997

Synthesis for Testability by Two-Clock Control.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

A Prototype for Adaptive Association of Street Names with Streets on Maps.

[BibT_eX]

[DOI]

Proceedings of the Graphics Recognition, 1997

1996

Improving Circuit Testability by Clock Control.

[BibT_eX]

[DOI]

Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

1995

A switch-level test generation system for synchronous and asynchronous circuits.

[BibT_eX]

[DOI]

J. Electron. Test., 1995

Conference Reports.

[BibT_eX]

N. Ranganathan

Sivaramakrishnan Venkatraman

IEEE Des. Test Comput., 1995

Programming pipelined CAD applications on message-passing architectures.

[BibT_eX]

[DOI]

Concurr. Pract. Exp., 1995

Parallel test generation with low communication overhead.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

A trainable, single-pass algorithm for column segmentation.

[BibT_eX]

[DOI]

Don Sylwester

Proceedings of the Third International Conference on Document Analysis and Recognition, 1995

HGA: A Hardware-Based Genetic Algorithm.

[BibT_eX]

[DOI]

Stephen D. Scott

Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays, 1995

1994

Isolating symbols from connection lines in a class of engineering drawings.

[BibT_eX]

[DOI]

Yuhong Yu

Pattern Recognit., 1994

Logic Simulation Using an Asynchronous Parallel Discrete-Event Simulation Model on a SIMD Machine.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Conference on VLSI Design, 1994

1993

Accurate computation of field reject ratio based on fault latency.

[BibT_eX]

[DOI]

D. Das

IEEE Trans. Very Large Scale Integr. Syst., 1993

Syntactic Segmentation and Labeling of Digitized Pages from Technical Journals.

[BibT_eX]

[DOI]

Mahesh Viswanathan

IEEE Trans. Pattern Anal. Mach. Intell., 1993

Generating Tests for Delay Faults in Nonscan Circuits.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 1993

Clock partitioning for testability.

[BibT_eX]

[DOI]

Proceedings of the Third Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1993

1992

A Prototype Document Image Analysis System for Technical Journals.

[BibT_eX]

[DOI]

Mahesh Viswanathan

Computer, 1992

A Switch-Level Test Generation System.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Conference on VLSI Design, 1992

A New Method for Generating Tests for Delay Faults in Non-Scan Circuits.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Conference on VLSI Design, 1992

DynaTAPP: dynamic timing analysis with partial path activation in sequential circuits.

[BibT_eX]

[DOI]

Proceedings of the conference on European design automation, 1992

1991

Estimating the Quality of Manufactured Digital Sequential Circuits.

[BibT_eX]

[DOI]

Dharam Vir Das

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

1990

A Statistical Theory of Digital Circuit Testability.

[BibT_eX]

[DOI]

Hassan Farhat

IEEE Trans. Computers, 1990

High-level microprogramming: an optimizing C compiler for a processing element of a CAD accelerator.

[BibT_eX]

[DOI]

Paul Kenyon

Proceedings of the 23rd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1990

An experimental study on reject ratio prediction for VLSI circuits: Kokomo revisited.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

1989

Signal Probabilities in AND-OR Trees.

[BibT_eX]

[DOI]

Lester Lipsky

IEEE Trans. Computers, 1989

Design of Parity Testable Combinational Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1989

A new model for computation of probabilistic testability in combinational circuits.

[BibT_eX]

[DOI]

Integr., 1989

Testability Analysis of Synchronous Sequential Circuits Based on Structural Data.

[BibT_eX]

[DOI]

Raghu V. Hudli

Proceedings of the Proceedings International Test Conference 1989, 1989

1988

A fast fault simulation algorithm for combinational circuits.

[BibT_eX]

[DOI]

Wuudiann Ke

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

1987

Decoding Substitution Ciphers by Means of Word Matching with Application to OCR.

[BibT_eX]

[DOI]

IEEE Trans. Pattern Anal. Mach. Intell., 1987

1985

Predicting Fault Coverage from Probabilistic Testability.

[BibT_eX]

Proceedings of the Proceedings International Test Conference 1985, 1985

1984

Characterizing the LSI Yield Equation from Wafer Test Data.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984

An Analysis of the Use of Rademacher-Walsh Spectrum in Compact Testing.

[BibT_eX]

[DOI]

Ten-Chuan Hsiao

IEEE Trans. Computers, 1984

1983

A Simplified Method to Calculate Failure Times in Fault-Tolerant Systems.

[BibT_eX]

[DOI]

Lester Lipsky

IEEE Trans. Computers, 1983

1981

A Graph Model for Pattern-Sensitive Faults in Random Access Memories.

[BibT_eX]

[DOI]

K. Narayanaswamy

IEEE Trans. Computers, 1981

LSI product quality and fault coverage.

[BibT_eX]

[DOI]

Proceedings of the 18th Design Automation Conference, 1981

1978

On Combinational Networks with Restricted Fan-Out.

[BibT_eX]

[DOI]

Kolar L. Kodandapani

IEEE Trans. Computers, 1978

1977

Diagnosis of Faults in Linear Tree Networks.

[BibT_eX]

[DOI]

Kolar L. Kodandapani

IEEE Trans. Computers, 1977

On a Relation Between Algebraic Programs and Turing Machines.

[BibT_eX]

[DOI]

James M. Steckelberg

Inf. Process. Lett., 1977

1970

Fault Testing in Combinational Cellular Arrays

[BibT_eX]

[DOI]