Shaolin Xie

According to our database, Shaolin Xie authored at least 14 papers between 2016 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

QuIT your B+-tree for the Quick Insertion Tree.

Aneesh Raman, Konstantinos Karatsenidis, Shaolin Xie, Matthaios Olma, Subhadeep Sarkar, Manos Athanassoulis

Proceedings of the Proceedings 28th International Conference on Extending Database Technology, 2025

2024

Scalable, Programmable and Dense: The HammerBlade Open-Source RISC-V Manycore.

Dai Cheol Jung, Max Ruttenberg, Paul Gao, Scott Davidson, Daniel Petrisko, Kangli Li, Aditya K. Kamath, Lin Cheng, Shaolin Xie, Peitian Pan, Zhongyuan Zhao, Zichao Yue, Bandhav Veluri, Sripathi Muralitharan, Adrian Sampson, Andrew Lumsdaine, Zhiru Zhang, Christopher Batten, Mark Oskin, Dustin Richmond, Michael Bedford Taylor

Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024

2020

A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator.

Dong-Hyeon Park, Subhankar Pal, Siying Feng, Paul Gao, Jielun Tan, Austin Rovinski, Shaolin Xie, Chun Zhao, Aporva Amarnath, Timothy Wesley, Jonathan Beaumont, Kuan-Yu Chen, Chaitali Chakrabarti, Michael Bedford Taylor, Trevor N. Mudge, David T. Blaauw, Hun-Seok Kim, Ronald G. Dreslinski

IEEE J. Solid State Circuits, 2020

2019

A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.

Austin Rovinski, Chun Zhao, Khalid Al-Hawaj, Paul Gao, Shaolin Xie, Christopher Torng, Scott Davidson, Aporva Amarnath, Luis Vega, Bandhav Veluri, Anuj Rao, Tutu Ajayi, Julian Puscar, Steve Dai, Ritchie Zhao, Dustin Richmond, Zhiru Zhang, Ian Galton, Christopher Batten, Michael B. Taylor, Ronald G. Dreslinski

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm.

Subhankar Pal, Dong-Hyeon Park, Siying Feng, Paul Gao, Jielun Tan, Austin Rovinski, Shaolin Xie, Chun Zhao, Aporva Amarnath, Timothy Wesley, Jonathan Beaumont, Kuan-Yu Chen, Chaitali Chakrabarti, Michael B. Taylor, Trevor N. Mudge, David T. Blaauw, Hun-Seok Kim, Ronald G. Dreslinski

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2018

Extreme Datacenter Specialization for Planet-Scale Computing: ASIC Clouds.

Shaolin Xie, Scott Davidson, Ikuo Magaki, Moein Khazraee, Luis Vega, Lu Zhang, Michael B. Taylor

ACM SIGOPS Oper. Syst. Rev., 2018

The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips.

Scott Davidson, Shaolin Xie, Christopher Torng, Khalid Al-Hawaj, Austin Rovinski, Tutu Ajayi, Luis Vega, Chun Zhao, Ritchie Zhao, Steve Dai, Aporva Amarnath, Bandhav Veluri, Paul Gao, Anuj Rao, Gai Liu, Rajesh K. Gupta, Zhiru Zhang, Ronald G. Dreslinski, Christopher Batten, Michael B. Taylor

IEEE Micro, 2018

The BaseJump Manycore Accelerator Network.

Shaolin Xie, Michael B. Taylor

CoRR, 2018

Parallel Polar Encoding in 5G Communication.

Yang Guo, Shaolin Xie, Zijun Liu, Lei Yang, Donglin Wang

Proceedings of the 2018 IEEE Symposium on Computers and Communications, 2018

Fast and Efficient Deep Sparse Multi-Strength Spiking Neural Networks with Dynamic Pruning.

Ruizhi Chen, Hong Ma, Shaolin Xie, Peng Guo, Pin Li, Donglin Wang

Proceedings of the 2018 International Joint Conference on Neural Networks, 2018

Low Latency Spiking ConvNets with Restricted Output Training and False Spike Inhibition.

Ruizhi Chen, Hong Ma, Peng Guo, Shaolin Xie, Pin Li, Donglin Wang

Proceedings of the 2018 International Joint Conference on Neural Networks, 2018

FBNA: A Fully Binarized Neural Network Accelerator.

Peng Guo, Hong Ma, Ruizhi Chen, Pin Li, Shaolin Xie, Donglin Wang

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2017

A self-indexed register file for efficient arithmetical computing hardware.

Lei Yang, Shaolin Xie, Zijun Liu, Xueliang Du, Donglin Wang

Proceedings of the 2017 9th Computer Science and Electronic Engineering Conference, 2017

2016

MaPU: A novel mathematical computing architecture.

Donglin Wang, Xueliang Du, Leizu Yin, Chen Lin, Hong Ma, Weili Ren, Huijuan Wang, Xingang Wang, Shaolin Xie, Lei Wang, Zijun Liu, Tao Wang, Zhonghua Pu, Guangxin Ding, Mengchen Zhu, Lipeng Yang, Ruoshan Guo, Zhiwei Zhang, Xiao Lin, Jie Hao, Yongyong Yang, Wenqin Sun, Fabiao Zhou, NuoZhou Xiao, Qian Cui, Xiaoqin Wang

Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016