Shaolan Li
Orcid: 0000-0002-2736-5451
According to our database1,
Shaolan Li
authored at least 45 papers
between 2016 and 2025.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2025
A 1.11 mm<sup>2</sup> IVUS SoC With $\pm 50^{\circ}$-Range Plane Wave Transmit Beamforming at 40 MHz.
IEEE Trans. Biomed. Circuits Syst., February, 2025
IEEE Trans. Very Large Scale Integr. Syst., January, 2025
2024
IEEE J. Solid State Circuits, March, 2024
An 82dB-SNDR Input-Driving-Relaxed Noise-Shaping SAR with Amplifier-Reused In-Loop Buffering and NTF Leakage Reshaping.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
2023
A Systematic and Innovative Six-in-One Evaluation Framework to Drive the Development of Future Hidden Champions.
Proceedings of the Distributed, Ambient and Pervasive Interactions, 2023
A 1.11 mm<sup>2</sup> Guidewire IVUS SoC with ±50°-Range Plane Wave Transmit Beamforming.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
Enabling Ultra-Low Power Ultrasound Imaging with Compute-in-Memory Sparse Reconstruction Accelerator.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2023
2022
Design and Optimization of Non-Volatile Capacitive Crossbar Array for In-Memory Computing.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
An 84-dB-SNDR Low-OSR Fourth-Order Noise-Shaping SAR With an FIA-Assisted EF-CRFF Structure and Noise-Mitigated Push-Pull Buffer-in-Loop Technique.
IEEE J. Solid State Circuits, 2022
Adv. Intell. Syst., 2022
An 84dB-SNDR Low-OSR 4<sup>th</sup>-Order Noise-Shaping SAR with an FIA-Assisted EF-CRFF Structure and Noise-Mitigated Push-Pull Buffer-in-Loop Technique.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
A 13.8-ENOB Fully Dynamic Third-Order Noise-Shaping SAR ADC in a Single-Amplifier EF-CIFF Structure With Hardware-Reusing kT/C Noise Cancellation.
IEEE J. Solid State Circuits, 2021
MAGICAL: An Open- Source Fully Automated Analog IC Layout System from Netlist to GDSII.
IEEE Des. Test, 2021
27.3 A 13.8-ENOB 0.4pF-CIN 3<sup>rd</sup>-Order Noise-Shaping SAR in a Single-Amplifier EF-CIFF Structure with Fully Dynamic Hardware-Reusing kT/C Noise Cancelation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Proceedings of the IEEE International Memory Workshop, 2021
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2020
A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL Structure in 40-nm CMOS.
IEEE J. Solid State Circuits, 2020
A 0.025-mm<sup>2</sup> 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL- ΔΣ M Structure.
IEEE J. Solid State Circuits, 2020
A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier.
IEEE J. Solid State Circuits, 2020
IEEE J. Solid State Circuits, 2020
An OTA-Less Second-Order VCO-Based CT $\Delta\Sigma$ Modulator Using an Inherent Passive Integrator and Capacitive Feedback.
IEEE J. Solid State Circuits, 2020
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
IEEE J. Solid State Circuits, 2019
A 0.029-mm<sup>2</sup> 17-fJ/Conversion-Step Third-Order CT ΔΣ ADC With a Single OTA and Second-Order Noise-Shaping SAR Quantizer.
IEEE J. Solid State Circuits, 2019
IEICE Trans. Electron., 2019
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A 0.01mm<sup>2</sup> 25µW 2MS/s 74dB-SNDR Continuous-Time Pipelined-SAR ADC with 120fF Input Capacitor.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Proceedings of the 2019 International Symposium on Physical Design, 2019
Proceedings of the International Conference on Computer-Aided Design, 2019
MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited Paper.
Proceedings of the International Conference on Computer-Aided Design, 2019
WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
A 0.025-mm<sup>2</sup> 0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
2018
A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure.
IEEE J. Solid State Circuits, 2018
A 0.029MM2 17-FJ/Conv.-Step CT $\Delta\Sigma$ ADC with 2<sup>nd</sup>-Order Noise-Shaping SAR Quantizer.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
A 13-ENOB 2<sup>nd</sup>-order noise-shaping SAR ADC realizing optimized NTF zeros using an error-feedback structure.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
A 174.3-dB FoM VCO-Based CT ΔΣ Modulator With a Fully-Digital Phase Extended Quantizer and Tri-Level Resistor DAC in 130-nm CMOS.
IEEE J. Solid State Circuits, 2017
Hierarchical and Analytical Placement Techniques for High-Performance Analog Circuits.
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017
A Scaling Compatible, Synthesis Friendly VCO-based Delta-sigma ADC Design and Synthesis Methodology.
Proceedings of the 54th Annual Design Automation Conference, 2017
2016
A 174.3dB FoM VCO-based CT ΔΣ modulator with a fully digital phase extended quantizer and tri-level resistor DAC in 130nm CMOS.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016