Shaogang Hu

Orcid: 0000-0002-8653-2491

According to our database1, Shaogang Hu authored at least 25 papers between 2013 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2024
Spatio-Temporal Fusion Spiking Neural Network for Frame-Based and Event-Based Camera Sensor Fusion.
IEEE Trans. Emerg. Top. Comput. Intell., June, 2024

Floating-Point Approximation Enabling Cost-Effective and High-Precision Digital Implementation of FitzHugh-Nagumo Neural Networks.
IEEE Trans. Biomed. Circuits Syst., April, 2024

Fullerene-Inspired Efficient Neuromorphic Network-on-Chip Scheme.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

Design and Implementation of a Hybrid, ADC/DAC-Free, Input-Sparsity-Aware, Precision Reconfigurable RRAM Processing-in-Memory Chip.
IEEE J. Solid State Circuits, February, 2024

A&B BNN: Add&Bit-Operation-Only Hardware-Friendly Binary Neural Network.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2024

2023
Achieving High Core Neuron Density in a Neuromorphic Chip Through Trade-off Among Area, Power Consumption, and Data Access Bandwidth.
IEEE Trans. Biomed. Circuits Syst., December, 2023

An efficient pruning and fine-tuning method for deep spiking neural network.
Appl. Intell., December, 2023

Batch normalization-free weight-binarized SNN based on hardware-saving IF neuron.
Neurocomputing, August, 2023

Ultra-High-Speed Accelerator Architecture for Convolutional Neural Network Based on Processing-in-Memory Using Resistive Random Access Memory.
Sensors, March, 2023

An Area- and Energy-Efficient Spiking Neural Network With Spike-Time-Dependent Plasticity Realized With SRAM Processing-in-Memory Macro and On-Chip Unsupervised Learning.
IEEE Trans. Biomed. Circuits Syst., February, 2023

ResNet-TCN: A Joint Model for ECG Heartbeat Classification with High Accuracy.
Proceedings of the International Conference on Information Networking, 2023

2022
A Co-Designed Neuromorphic Chip With Compact (17.9K F<sup>2</sup>) and Weak Neuron Number-Dependent Neuron/Synapse Modules.
IEEE Trans. Biomed. Circuits Syst., December, 2022

2021
Quantized STDP-based online-learning spiking neural network.
Neural Comput. Appl., 2021

Direct training of hardware-friendly weight binarized spiking neural network with surrogate gradient learning towards spatio-temporal event-based dynamic data recognition.
Neurocomputing, 2021

Design of a constant loop bandwidth phase-locked loop based on artificial neural network.
IEICE Electron. Express, 2021

2020
Application of Deep Compression Technique in Spiking Neural Network Chip.
IEEE Trans. Biomed. Circuits Syst., 2020

An energy-efficient deep convolutional neural networks coprocessor for multi-object detection.
Microelectron. J., 2020

STBNN: Hardware-friendly spatio-temporal binary neural network with high pattern recognition accuracy.
Neurocomputing, 2020

2019
A Neuromorphic-Hardware Oriented Bio-Plausible Online-Learning Spiking Neural Network Model.
IEEE Access, 2019

Implementation of a Low Noise Amplifier With Self-Recovery Capability.
IEEE Access, 2019

Study of Recall Time of Associative Memory in a Memristive Hopfield Neural Network.
IEEE Access, 2019

Design of a Neural Network-Based VCO With High Linearity and Wide Tuning Range.
IEEE Access, 2019

2018
Predicting House Price With a Memristor-Based Artificial Neural Network.
IEEE Access, 2018

Realization of a Power-Efficient Transmitter Based on Integrated Artificial Neural Network.
IEEE Access, 2018

2013
Vco-Based continuous-Time Sigma Delta ADC Based on a Dual-VCO-quantizer-Loop Structure.
J. Circuits Syst. Comput., 2013


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