Shantharam Kalipatnapu

Orcid: 0000-0001-8457-2214

According to our database1, Shantharam Kalipatnapu authored at least 5 papers between 2019 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Links

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Bibliography

2024
Low-latency machine learning FPGA accelerator for multi-qubit state discrimination.
CoRR, 2024

2023
SQ-CARS: A Scalable Quantum Control and Readout System.
IEEE Trans. Instrum. Meas., 2023

2021
High speed VLSI architecture for improved region based active contour segmentation technique.
Integr., 2021

2020
Low-Complexity Interval Passing Algorithm and VLSI Architecture for Binary Compressed Sensing.
IEEE Trans. Very Large Scale Integr. Syst., 2020

2019
High-throughput Bit Flipping decoder for structured LDPC codes.
IET Commun., 2019


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