Shantanu Sarangi
According to our database1,
Shantanu Sarangi
authored at least 13 papers
between 2011 and 2024.
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Bibliography
2024
A Scalable & Cost Efficient Next-Gen Scan Architecture: Streaming Scan Test via NVIDIA MATHS.
Proceedings of the IEEE International Test Conference, 2024
2023
IEEE Des. Test, August, 2023
2022
Proceedings of the 40th IEEE VLSI Test Symposium, 2022
On-Die Noise Measurement During Automatic Test Equipment (ATE) Testing and In-System-Test (IST).
Proceedings of the 40th IEEE VLSI Test Symposium, 2022
2020
2019
Hybrid Performance Modeling for Optimization of In-System-Structural-Test (ISST) Latency.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019
Proceedings of the 37th IEEE VLSI Test Symposium, 2019
An Efficient Supervised Learning Method to Predict Power Supply Noise During At-speed Test.
Proceedings of the IEEE International Test Conference, 2019
2017
Proceedings of the 35th IEEE VLSI Test Symposium, 2017
2016
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
Proceedings of the 2016 IEEE International Test Conference, 2016
2011
A clock-gating based capture power droop reduction methodology for at-speed scan testing.
Proceedings of the Design, Automation and Test in Europe, 2011