Shantanu Rajwade
According to our database1,
Shantanu Rajwade
authored at least 4 papers
between 2010 and 2023.
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Bibliography
2023
A 1.67Tb, 5b/Cell Flash Memory Fabricated in 192-Layer Floating Gate 3D-NAND Technology and Featuring a 23.3Gb/mm2 Bit Density.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2021
A 1Tb 4b/Cell 144-Tier Floating-Gate 3D-NAND Flash Memory with 40MB/s Program Throughput and 13.8Gb/mm<sup>2</sup> Bit Density.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2011
Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2011), 2011
2010
Low power nonvolatile SRAM circuit with integrated low voltage nanocrystal PMOS Flash.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010