Shanshi Huang
Orcid: 0000-0002-1760-7656
According to our database1,
Shanshi Huang
authored at least 26 papers
between 2019 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
Voxel-CIM: An Efficient Compute-in-Memory Accelerator for Voxel-based Point Cloud Neural Networks.
CoRR, 2024
CoRR, 2024
2023
ENNA: An Efficient Neural Network Accelerator Design Based on ADC-Free Compute-In-Memory Subarrays.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023
Reliability and Security of Compute-In-Memory Based Deep Neural Network Accelerators.
PhD thesis, 2023
ACM Trans. Design Autom. Electr. Syst., 2023
2022
Achieving High In Situ Training Accuracy and Energy Efficiency with Analog Non-Volatile Synaptic Devices.
ACM Trans. Design Autom. Electr. Syst., 2022
Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips.
IEEE J. Solid State Circuits, 2022
A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-Verify, and Temperature-Independent ADC References.
IEEE J. Solid State Circuits, 2022
IEEE Des. Test, 2022
A 40nm Analog-Input ADC-Free Compute-in-Memory RRAM Macro with Pulse-Width Modulation between Sub-arrays.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
2021
Secure XOR-CIM Engine: Compute-In-Memory SRAM Architecture With Embedded XOR Encryption.
IEEE Trans. Very Large Scale Integr. Syst., 2021
A Runtime Reconfigurable Design of Compute-in-Memory-Based Hardware Accelerator for Deep Learning Inference.
ACM Trans. Design Autom. Electr. Syst., 2021
DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-Chip Training.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Mitigating Adversarial Attack for Compute-in-Memory Accelerator Utilizing On-chip Finetune.
Proceedings of the 10th IEEE Non-Volatile Memory Systems and Applications Symposium, 2021
Exploiting Process Variations to Protect Machine Learning Inference Engine from Chip Cloning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A 40nm RRAM Compute-in-Memory Macro Featuring On-Chip Write-Verify and Offset-Cancelling ADC References.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Secure-RRAM: A 40nm 16kb Compute-in-Memory Macro with Reconfigurability, Sparsity Control, and Embedded Security.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2020
CIMAT: A Compute-In-Memory Architecture for On-chip Training Based on Transpose SRAM Arrays.
IEEE Trans. Computers, 2020
15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Overcoming Challenges for Achieving High in-situ Training Accuracy with Emerging Memories.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
2019
CIMAT: a transpose SRAM-based compute-in-memory architecture for deep neural network on-chip training.
Proceedings of the International Symposium on Memory Systems, 2019